Visible to the public Leveraging All-Spin Logic to Improve Hardware Security

TitleLeveraging All-Spin Logic to Improve Hardware Security
Publication TypeConference Paper
Year of Publication2017
AuthorsAlasad, Qutaiba, Yuan, Jiann, Fan, Deliang
Conference NameProceedings of the on Great Lakes Symposium on VLSI 2017
PublisherACM
Conference LocationNew York, NY, USA
ISBN Number978-1-4503-4972-7
Keywordsasl., Collaboration, composability, ic protection, IP piracy, ip protection, logic encryption, policy, policy-based governance, pubcrawl, Resiliency, spintronic device
Abstract

Due to the globalization of Integrated Circuit (IC) design in the semiconductor industry and the outsourcing of chip manufacturing, third Party Intellectual Properties (3PIPs) become vulnerable to IP piracy, reverse engineering, counterfeit IC, and hardware trojans. A designer has to employ a strong technique to thwart such attacks, e.g. using Strong Logic Locking method [1]. But, such technique cannot be used to protect some circuits since the inserted key-gates rely on the topology of the circuit. Also, it requires higher power, delay, and area overheads compared to other techniques. In this paper, we present the use of spintronic devices to help protect ICs with less performance overhead. We then evaluate the proposed design based on security metric and performance overhead. One of the best spintronic device candidates is the All Spin Logic due to its unique properties: small area, no spin-charge signal conversion, and its compatibility with conventional CMOS technology.

URLhttp://doi.acm.org/10.1145/3060403.3060471
DOI10.1145/3060403.3060471
Citation Keyalasad_leveraging_2017