Post-doctoral Position at INRIA Grenoble

Proposal for a Post-doctoral Position at INRIA Grenoble

Title
=====

Advanced dataflow programming
Model of computation and parallel schedule generation.


Programmation flot de donnees avancee
Modele de calcul et generation d'ordonnancement paralleles


Location, supervisors, duration
================================

INRIA Grenoble (France), Spades Team

Pascal FRADET Alain GIRAULT
pascal.fradet@inria.fr alain.girault@inria.fr

The postdoc position is for 1 year, starting end of 2014 (October ideally)

Salary: 2.620 euros gross monthly (about 2.135 euros net).

Abstract
========

We are interested in dataflow models of computation to program applications for manycore chips. In order to ensure analysis and scheduling, the synchronous dataflow model (SDF) is widely used because it allows static analyses (liveness and buffer boundedness) and scheduling. SDF has a clean semantics and leads to efficient implementations but it cannot express many dynamic features. In particular, it cannot express dynamic I/O rate modifications, nor dynamic topology modifications. For this reason, many variants of SDF have been proposed, among which we can cite BDF, CSDF, HDF, VRDF, PSDF, and SPDF.

We have recently proposed BPDF [1], a dataflow model with integer and boolean parameters able to express dynamicity while remaining verifiable and schedulable. Integer parameters define rate modifications while boolean parameters specify some dynamic topology modifications (activation and deactivation of dataflow edges).

The postdoctoral project will focus on extending the expressivity of BPDF and/or study multi-criteria scheduling of the model on multi-core platforms.

• possible extensions of BPDF are more expressive changes of the topology (e.g., adding/removing actors and edges). Since the model of computation should remain analysable for liveness and boundedness, such linguistic extensions usually entails extensions of the corresponding analyses.
• parallel schedules of BPDF dataflow applications for manycore chips can be generated according several criteria: throughput (useful for streaming application), input-output latency (useful for real-time applications), power consumption (useful for autonomous applications), to cite a few. One of the difficulty here resides in multi-criteria scheduling with antagonistic criteria./li>

Required Skills
===============

A PhD in formal methods, embedded systems, and/or real-time programming (e.g., analysis, semantics, verification, validation, code generation, ...). A knowledge of dataflow programming and/or scheduling would be a plus.

Send CV + contact information of 2 or 3 recommenders to Pascal Fradet and Alain Girault.

References
==========

[1] Vagelis Bebelis, Pascal Fradet, Alain Girault, Bruno Lavigueur:
"BPDF: A Statically Analyzable Dataflow Model with Integer and
Boolean Parameters"; In International Conference on Embedded
Software, EMSOFT'13, September 2013.