Compact Oscillation Neuron Exploiting Metal-insulator-transition for Neuromorphic Computing
Title | Compact Oscillation Neuron Exploiting Metal-insulator-transition for Neuromorphic Computing |
Publication Type | Conference Paper |
Year of Publication | 2016 |
Authors | Chen, Pai-Yu, Seo, Jae-sun, Cao, Yu, Yu, Shimeng |
Conference Name | Proceedings of the 35th International Conference on Computer-Aided Design |
Publisher | ACM |
Conference Location | New York, NY, USA |
ISBN Number | 978-1-4503-4466-1 |
Keywords | metal-insulator-transition, Metrics, neuromorphic computing, neuron, oscillating behaviors, oscillation, pubcrawl, Resiliency, resistive memory, synaptic array |
Abstract | The phenomenon of metal-insulator-transition (MIT) in strongly correlated oxides, such as NbO2, have shown the oscillation behavior in recent experiments. In this work, the MIT based two-terminal device is proposed as a compact oscillation neuron for the parallel read operation from the resistive synaptic array. The weighted sum is represented by the frequency of the oscillation neuron. Compared to the complex CMOS integrate-and-fire neuron with tens of transistors, the oscillation neuron achieves significant area reduction, thereby alleviating the column pitch matching problem of the peripheral circuitry in resistive memories. Firstly, the impact of MIT device characteristics on the weighted sum accuracy is investigated when the oscillation neuron is connected to a single resistive synaptic device. Secondly, the array-level performance is explored when the oscillation neurons are connected to the resistive synaptic array. To address the interference of oscillation between columns in simple cross-point arrays, a 2-transistor-1-resistor (2T1R) array architecture is proposed at negligible increase in array area. Finally, the circuit-level benchmark of the proposed oscillation neuron with the CMOS neuron is performed. At single neuron node level, oscillation neuron shows textgreater12.5X reduction of area. At 128x128 array level, oscillation neuron shows a reduction of ~4% total area, textgreater30% latency, ~5X energy and ~40X leakage power, demonstrating its advantage of being integrated into the resistive synaptic array for neuro-inspired computing. |
URL | http://doi.acm.org/10.1145/2966986.2967015 |
DOI | 10.1145/2966986.2967015 |
Citation Key | chen_compact_2016 |