Enhancing Hardware Security with Emerging Transistor Technologies
| Title | Enhancing Hardware Security with Emerging Transistor Technologies |
| Publication Type | Conference Paper |
| Year of Publication | 2016 |
| Authors | Bi, Yu, Hu, X. Sharon, Jin, Yier, Niemier, Michael, Shamsi, Kaveh, Yin, Xunzhao |
| Conference Name | Proceedings of the 26th Edition on Great Lakes Symposium on VLSI |
| Date Published | May 2016 |
| Publisher | ACM |
| Conference Location | New York, NY, USA |
| ISBN Number | 978-1-4503-4274-2 |
| Keywords | emerging transistors, hardware security, i-o systems security, i/o systems security, IC camouflaging, io systems security, NCFET, polymorphic logic, pubcrawl, Scalability, symFET, TFET, tunnel transistor |
| Abstract | We consider how the I-V characteristics of emerging transistors (particularly those sponsored by STARnet) might be employed to enhance hardware security. An emphasis of this work is to move beyond hardware implementations of physically unclonable functions (PUFs) and random num- ber generators (RNGs). We highlight how new devices (i) may enable more sophisticated logic obfuscation for IP protection, (ii) could help to prevent fault injection attacks, (iii) prevent differential power analysis in lightweight cryptographic systems, etc. |
| URL | https://dl.acm.org/doi/10.1145/2902961.2903041 |
| DOI | 10.1145/2902961.2903041 |
| Citation Key | bi_enhancing_2016 |