The use of outsourcing in silicon manufacturing has rendered hardware susceptible to malicious bugs, called Trojans, that can cause an Integrated Circuit (IC) to fail in the field, similar to the way viruses manifest themselves in software. While there has been significant inroads into Trojan detection and diagnosis in the recent past, high-resolution Trojan detection has been hampered by the increased variability in silicon manufacturing processes, allowing Trojans to hide behind the design guardbands necessitated by process variability effects. The key objective of this research is to develop techniques, algorithms and support infrastructure for detecting, diagnosing and mitigating the effects of Trojans in a variety of circuits that can cause system malfunction after deployment in the field, in the presence of process variability effects. The underlying Trojan detection techniques for both mixed-signal and digital circuits use test stimulus optimization algorithms that maximize the sensitivities of the tests applied to the presence of malicious hardware Trojans. Such algorithms are supported by hardware for delivering the tests to vulnerable hardware designs in the field. Since the nature of bugs inserted maliciously into chip designs is not known apriori, the investigators use on-the-fly learning algorithms to refine the applied tests to expose the effects of inserted Trojans. In addition, precomputed and side-channel tests are applied to increase overall test effectiveness by up to 30X over existing methods. These techniques will enable significantly increased security of US industrial and government intellectual property and prevent tampering of US chip designs by external third parties.
SaTC: STARSS: Trojan Detection and Diagnosis in Mixed-Signal Systems Using On-The-Fly Learned, Precomputed and Side Channel Tests