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Nearly all security protocols rely on random numbers. A hardware True Random Number Generator (TRNG) is a circuit implemented within an Integrated Circuit (IC). If a TRNG is not truly random, an adversary may be able to break into the security of a protocol. Hence true randomness is an important property. TRNG circuits are often large and power hungry. There is a need for low-power TRNG in battery operated devices or in energy constrained environments. This proposal addresses that need. The proposed research explores an alternative to traditional TRNG designs. Instead of taking on considerable design complexity and energy dissipation by directly turning circuits to generate high quality random numbers, it starts with a sufficiently good physical circuit random number generator, and then combines it with a robust low-power statistical post-processing unit to address both bias, and correlation between TRNG outputs. This results in a design where the first component is only required to provide some randomness, while the second component refines this randomness through decorrelation and bias removal to extract provably perfectly random sequence of bits akin to identical and independent fair coin flips. This design will be implemented in a silicon prototype. The proposed research is interdisciplinary involving applied probability, network security, and VLSI design.
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SaTC: STARSS: Small: Design of Low-Power True Random Number Generator based on Adaptive Post-Processing