Biblio

The core operation of public-key cryptosystem e.g. elliptic curve cryptography (ECC) is the modular multiplication. It is the heavy computational block and the most costly cryptographic operation. Area-Efficient hardware architecture of 256-bit modified interleaved modular multiplication (IMM) is represented in this research. The novelty of this work is the device area minimization with keeping computational time as minimum as possible i.e., 2.09 μs for ECC with Koblitz Curve. In this research, IMM is implemented using a fewer number of resources such as 421 slices, 514 FF pairs, 522 registers, 1770 LUTs, and 1463 LUT-FF pairs. This hardware implementation provides a maximum frequency of 122.883 MHz and area-time (AT) product 0.879 and throughput rate 122.49 Mbps on Virtex-7 FPGA technology which is better than the other related recent works. The proposed design saves approximately 61.75% to 93.16% slice LUTs, 95.76% to 133.69% LUT-FF pairs, and 103.8% to 168.65% occupied slices on the Virtex-7 FPGA for the 256-bit prime field. This proposed hardware implementation design also keeps less AT product which is the most crucial parameter for ECC operation. To our best knowledge, this design provides better performance than the recently available designs for IMM for ECC operation.

Differential Power Analysis (DPA) attacks were shown to be effective in recovering the secret key information from a variety cryptographic systems. In response, several design methods, ranging from the cell level to the algorithmic level, have been proposed to defend against DPA attacks. Cell level solutions depend on DPA resistant cell designs which attempt to minimize power variance during transitions while minimizing area and power consumption. In this paper, we discuss how a differential circuit design style is incorporated into a COTS tool set, resulting in a fully automated synthesis system DPA resistant integrated circuits. Based on the Secure Differential Multiplexer Logic (SDMLp), this system can be used to synthesize complete cryptographic processors which provide strong defense against DPA while minimizing area and power overhead. We discuss how both combinational and sequential cells are incorporated in the cell library. We show the effectiveness of the tool chain by using it to automatically synthesize the layouts, from RT level Verilog specifications, of both the DES and AES encryption ICs in 90nm CMOS. In each case, we present experimental data to demonstrate DPA attack resistance and area, power and performance overhead and compare these with circuits synthesized in another differential logic called MDPL as well as standard CMOS synthesis results.

Embedded electronic devices and sensors such as smartphones, smart watches, medical implants, and Wireless Sensor Nodes (WSN) are making the “Internet of Things” (IoT) a reality. Such devices often require cryptographic services such as authentication, integrity and non-repudiation, which are provided by Public-Key Cryptography (PKC). As these devices are severely resource-constrained, choosing a suitable cryptographic system is challenging. Pairing Based Cryptography (PBC) is among the best candidates to implement PKC in lightweight devices. In this research, we present a fast and energy efficient implementation of PBC based on Barreto-Naehrig (BN) curves and optimal Ate pairing using hardware/software co-design. Our solution consists of a hardware-based Montgomery multiplier, and pairing software running on an ARM Cortex A9 processor in a Zynq-7020 System-on-Chip (SoC). The multiplier is protected against simple power analysis (SPA) and differential power analysis (DPA), and can be instantiated with a variable number of processing elements (PE). Our solution improves performance (in terms of latency) over an open-source software PBC implementation by factors of 2.34 and 2.02, for 256- and 160-bit field sizes, respectively, as measured in the Zynq-7020 SoC.