Visible to the public Highly Area-Efficient Implementation of Modular Multiplication for Elliptic Curve Cryptography

TitleHighly Area-Efficient Implementation of Modular Multiplication for Elliptic Curve Cryptography
Publication TypeConference Paper
Year of Publication2020
AuthorsRahman, M. S., Hossain, M. S.
Conference Name2020 IEEE Region 10 Symposium (TENSYMP)
Date Publishedjun
Keywords256-bit modified interleaved modular multiplication, Computer architecture, cryptographic operation, cryptography, ECC operation, Elliptic curve cryptography, Elliptic curve cryptography (ECC), Field Programmable Gate Array (FPGA), field programmable gate arrays, Flip-flops, Hardware, Hardware Architecture (HA), hardware implementation design, IMM, Interleaved Modular Multiplication (IMM), koblitz Curve, logic design, LUT-FF pairs, Metrics, multiplying circuits, pubcrawl, public key cryptography, Public Key Cryptography (PKC), public-key cryptosystem, Registers, Resiliency, Scalability, Table lookup, Throughput, Virtex-7 FPGA technology
AbstractThe core operation of public-key cryptosystem e.g. elliptic curve cryptography (ECC) is the modular multiplication. It is the heavy computational block and the most costly cryptographic operation. Area-Efficient hardware architecture of 256-bit modified interleaved modular multiplication (IMM) is represented in this research. The novelty of this work is the device area minimization with keeping computational time as minimum as possible i.e., 2.09 ms for ECC with Koblitz Curve. In this research, IMM is implemented using a fewer number of resources such as 421 slices, 514 FF pairs, 522 registers, 1770 LUTs, and 1463 LUT-FF pairs. This hardware implementation provides a maximum frequency of 122.883 MHz and area-time (AT) product 0.879 and throughput rate 122.49 Mbps on Virtex-7 FPGA technology which is better than the other related recent works. The proposed design saves approximately 61.75% to 93.16% slice LUTs, 95.76% to 133.69% LUT-FF pairs, and 103.8% to 168.65% occupied slices on the Virtex-7 FPGA for the 256-bit prime field. This proposed hardware implementation design also keeps less AT product which is the most crucial parameter for ECC operation. To our best knowledge, this design provides better performance than the recently available designs for IMM for ECC operation.
DOI10.1109/TENSYMP50017.2020.9230990
Citation Keyrahman_highly_2020