Biblio

Logic encryption is a popular Design-for-Security(DfS) solution that offers protection against the potential adversaries in the third-party fab labs and end-users. However, over the years, logic encryption has been a target of several attacks, especially Boolean satisfiability attacks. This paper exploits SAT attack's inability of deobfuscating sequential circuits as a defense against it. We propose several strategies capable of preventing the SAT attack by obfuscating the scan-based Design-for-Testability (DfT) infrastructure. Unlike the existing SAT-resilient schemes, the proposed techniques do not suffer from poor output corruption for wrong keys. This paper also offers various probable solutions for inserting the key-gates into the circuit that ensures protection against numerous other attacks, which exploit weak key-gate locations. Along with several gate-level obfuscation strategies, this paper also presents a Cellular Automata (CA) guided FSM obfuscation strategy to offer protection at a higher abstraction level, that is, RTL-level. For all the proposed schemes, rigorous security analysis against various attacks evaluates their strengths and limitations. Testability analysis also ensures that none of the proposed techniques hamper the basic testing properties of the ICs. We also present a CA-based FSM watermarking strategy that helps to detect potential theft of the designer's IP by any adversary.

Two design techniques improve the robustness of Whitenoise encryption algorithm implementation to side-channel attacks based on dynamic and/or static power consumption. The first technique conceals the power consumption and has linear cost. The second technique randomizes the power consumption and has quadratic cost. These techniques are not mutually exclusive; their synergy provides a good robustness to power analysis attacks. Other circuit-level protection can be applied on top of the proposed techniques, opening the avenue for generating very robust implementations.

To accurately detect Hardware Trojans in integrated circuits design process, a machine-learning-based detection method at the register transfer level (RTL) is proposed. In this method, circuit features are extracted from the RTL source codes and a training database is built using circuits in a Hardware Trojans library. The training database is used to train an efficient detection model based on the gradient boosting algorithm. In order to expand the Hardware Trojans library for detecting new types of Hardware Trojans and update the detection model in time, a server-client mechanism is used. The proposed method can achieve 100% true positive rate and 89% true negative rate, on average, based on the benchmark from Trust-Hub.

There has been a growing expansion in the use of steganography, due to the evolution in using internet technology and multimedia technology. Hence, nowadays, the information is not secured sufficiently while transmitting it over the network. Therefore, information security has taken an important role to provide security against unauthorized individuals. This paper proposes steganography and cryptography technique to secure image based on hybrid edge detector. Cryptography technique is used to encrypt a secret image by using Vernam cipher algorithm. The robust of this algorithm is depending on pseudorandom key. Therefore, pseudo-random key is generated from a nonlinear feedback shift register (Geffe Generator). While in steganography, Hybrid Sobel and Kirch edge detector have been applied on the cover image to locate edge pixels. The least significant bit (LSB) steganography technique is used to embed secret image bits in the cover image in which 3 bits are embedded in edge pixel and 2 bits in smooth pixel. The proposed method can be used in multi field such as military, medical, communication, banking, Electronic governance, and so on. This method gives an average payload ratio of 1.96 with 41.5 PSNR on average. Besides, the maximum size of secret image that can be hidden in the cover image of size 512*512 is 262*261. Also, when hiding 64800 bits in baboon cover image of size 512*512, it gives PSNR of 50.42 and MSE of 0.59.

In this paper, We propose DNA sticker model based algorithm, a computability model, which is a simulation of the parallel computations using the Molecular computing as in Adelman's DNA computing experiment, it demonstrates how to use a sticker-based model to design a simple DNA-based algorithm for attacking a linear and a non-linear feedback shift register (FSR) based stream cipher. The algorithm first construct the TEST TUBE contains all overall solution space of memory complexes for the cipher and initials of registers via the sticker-based model. Then, with biological operations, separate and combine, we remove those which encode illegal plain and key stream from the TEST TUBE of memory complexes, the decision based on verifying a key stream bit this bit represented by output of LFSRs equation. The model anticipates two basic groups of single stranded DNA molecules in its representation one of a genetic bases and second of a bit string, It invests parallel search into the space of solutions through the possibilities of DNA computing and makes use of the method of cryptanalysis of algebraic code as a decision technique to accept the solution or not, and their operations are repeated until one solution or limited group of solutions is reached. The main advantages of the suggested algorithm are limited number of cipher characters, and finding one exact solution The present work concentrates on showing the applicability of DNA computing concepts as a powerful tool in breaking cryptographic systems.

This paper proposed a feedback shift register structure which can be split, it is based on a research of operating characteristics about 70 kinds of cryptographic algorithms and the research shows that the “different operations similar structure” reconfigurable design is feasible. Under the configuration information, the proposed structure can implement the multiplication in finite field GF(2n), the multiply/divide linear feedback shift register and other operations. Finally, this paper did a logic synthesis based on 55nm CMOS standard-cell library and the results show that the proposed structure gets a hardware resource saving of nearly 32%, the average power consumption saving of nearly 55% without the critical delay increasing significantly. Therefore, the “different operations similar structure” reconfigurable design is a new design method and the proposed feedback shift register structure can be an important processing unit for coarse-grained reconfigurable cryptologic array.

A5-1 algorithm is a stream cipher used to encrypt voice data in GSM, which needs to be realized with high performance due to real-time requirements. Traditional implementation on FPGA or ASIC can't obtain a trade-off among performance, cost and flexibility. To this aim, this paper introduces CGRCA to implement A5-1, and in order to optimize the performance and resource consumption, this paper proposes a resource-based path seeking (RPS) algorithm to develop an advanced implementation. Experimental results show that final optimal throughput of A5-1 implemented on CGRCA is 162.87Mbps when the frequency is 162.87MHz, and the set-up time is merely 87 cycles, which is optimal among similar works.

In this paper a novel data hiding method has been proposed which is based on Non-Linear Feedback Shift Register and Tinkerbell 2D chaotic map. So far, the major work in Steganography using chaotic map has been confined to image steganography where significant restrictions are there to increase payload. In our work, 2D chaotic map and NLFSR are used to developed a video steganography mechanism where data will be embedded in the segregated frames. This will increase the data hiding limit exponentially. Also, embedding position of each frame will be different from others frames which will increase the overall security of the proposed mechanism. We have achieved this randomized data hiding points by using a chaotic map. Basically, Chaotic theory which is non-linear dynamics physics is using in this era in the field of Cryptography and Steganography and because of this theory, little bit changes in initial condition makes the output totally different. So, it is very hard to get embedding position of data without knowing the initial value of the chaotic map.

The use of side-channel measurements and fingerprinting, in conjunction with statistical analysis, has proven to be the most effective method for accurately detecting hardware Trojans in fabricated integrated circuits. However, these post-fabrication trust evaluation methods overlook the capabilities of advanced design skills that attackers can use in designing sophisticated Trojans. To this end, we have designed a Trojan using power-gating techniques and demonstrate that it can be masked from advanced side-channel fingerprinting detection while dormant. We then propose a real-time trust evaluation framework that continuously monitors the on-board global power consumption to monitor chip trustworthiness. The measurements obtained corroborate our frameworks effectiveness for detecting Trojans. Finally, the results presented are experimentally verified by performing measurements on fabricated Trojan-free and Trojan-infected variants of a reconfigurable linear feedback shift register (LFSR) array.