This research project develops new hardware designs and implementations for a class of post-quantum secure cryptographic (PQC) algorithms. While today's algorithms used for public key cryptography, e.g. the RSA algorithm, or digital signatures are vulnerable to being broken through "cryptanalysis" using quantum computers, PQC algorithms offer protections from such cryptanalysis as they cannot be broken on a quantum computer. To understand how to create the most efficient hardware PQC designs from energy, area, and performance perspective, this project realizes the new algorithms as custom application specific integrated circuits. This work focuses on hardware design aspect of PQC algorithms that has been largely unexplored. This project especially promotes development and exchange of ideas between hardware security and integrated circuit researchers and among a broader audience through development of professional and educational activities. To advance the understanding of the PQC algorithms, this project develops FPGA implementations of the code-based algorithms for evaluation. Novel designs for modules such as Gaussian Elimination, or polynomial evaluation with Additive FFT are developed, to create new and efficient hardware primitives. The designs are taken through VLSI design flow to realize the integrated circuits that are evaluated for power, area, and performance. Issues of large memories, needed for the large keys used by the PQC algorithms, are addressed as well as incorporation of the integrated circuits with other computing platforms to create hardware accelerators for the PQC algorithms. This project may contribute to the ongoing US and international algorithm standardization efforts.
SaTC: CORE: Small: Collaborative: Hardware Architectures for Post-Quantum Cryptography