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Due to the prohibitive costs of semiconductor manufacturing, most computer chip design companies outsource their production to offshore foundries. As many of these chips may be manufactured in environments of limited trust, problems of the piracy of intellectual property (IP) and the overproduction of integrated circuits (ICs) have emerged in recent years. This project focuses on designing a secure logic locking technique to enable protection against untrusted IC manufacturing. The developed solution is resistant to all known attacks.
Logic locking is a promising solution for enabling trust in outsourced IC manufacturing, where a design is obfuscated by modifying the functionality. A locked chip will produce incorrect results unless activated by an obfuscation key. However, Boolean satisfiability (SAT)-based algorithms have been shown to effectively determine the obfuscation key and break the locking mechanisms. In this work, a novel secure cell (SC) is designed, which prevents the obfuscation key from being captured in internal flip-flops of a chip and disables scan dump after functional mode. The SC provides a complete protection against SAT-based and other existing attacks that utilize scan data. In addition, SC provides support for commercial tools to generate test patterns without having the obfuscation key. This will help perform the manufacturing test before the activation of chips, and thus preventing IC overproduction.
The proposed research will serve a critical need for the industry and government by working to support trust in the semiconductor manufacturing and test process. The integration of education and research is a key objective of this project. This research is multidisciplinary, linking the fields of IC design, simulation and test, hardware security, and embedded systems. The graduate and undergraduate students working on this project will receive interdisciplinary training across diverse areas of electrical and computer engineering. A novel upper-division course on hardware security for the graduate and undergraduate students will create a next-generation cybersecurity workforce for the government and commercial sectors.
The artifacts expected as outcomes from this project will be publicly accessible during the period of performance and afterwards. All peer-reviewed publications will be accessible through the link http://www.eng.auburn.edu/~uguin/publications.html. All raw input data, derived data and code versions needed for reproduction of results will be stored with the sources for the articles, so that third parties can reproduce the results. This will be maintained for all publications. If the data are large, a secure alternative means for sharing will be provided.
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CRII: SaTC: Robust Design-for-Security (DFS) Architecture for Enabling Trust in Integrated Circuits (IC) Manufacturing and Test