Skip to Main Content Area
  • CPS-VO
    • Contact Support
  • Browse
    • Calendar
    • Announcements
    • Repositories
    • Groups
  • Search
    • Search for Content
    • Search for a Group
    • Search for People
    • Search for a Project
    • Tagcloud
      
 
Not a member?
Click here to register!
Forgot username or password?
 
Home
National Science Foundation

Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

CPS-VO

hardware Trojan detection technique

biblio

Visible to the public Design, implementation and security analysis of Hardware Trojan Threats in FPGA

Submitted by BrandonB on Thu, 04/30/2015 - 1:41pm
  • integrated circuits
  • RoT
  • security
  • denial of service
  • design
  • encryption
  • field programmable gate arrays
  • FPGA testbed
  • Hardware
  • hardware Trojan detection technique
  • hardware Trojan threats
  • Hardware Trojans
  • HDM
  • HTT detectability metric
  • HTT detection
  • ICs
  • timing variation
  • integrated logic circuits
  • invasive software
  • missed detection probability
  • normalized physical parameters
  • optimal detection threshold
  • power consumption
  • Power demand
  • Resiliency
  • root of trust
  • Security analysis
  • sensitive information leak
  • summation of false alarm
  • timing
  • Trojan taxonomy
  • Trojan horses

Terms of Use  |  ©2023. CPS-VO