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National Science Foundation

Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

CPS-VO

lifting scheme algorithm

biblio

Visible to the public "Improved serial 2D-DWT processor for advanced encryption standard"

Submitted by grigby1 on Mon, 02/13/2017 - 1:08pm
  • Hardware
  • size 65 nm
  • serialized DT processor
  • serial 2D-DWT processor
  • secured image processing
  • RTL-GDSII
  • Quantization (signal)
  • pubcrawl170102
  • low power ASIC
  • lifting scheme algorithm
  • image data security
  • Image coding
  • high speed encryption
  • advanced encryption standard
  • frequency 333 MHz
  • encryption
  • DWT
  • discrete wavelet transforms
  • discrete wavelet transform
  • data compression
  • Cryptography
  • compression ratio
  • CMOS technology
  • ASIC circuit design
  • application specific integrated circuits
  • AES

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