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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
Built-In Test
biblio
Mitigating JTAG as an Attack Surface
Submitted by grigby1 on Fri, 08/28/2020 - 11:51am
private instructions
JTAG test access ports
JTAG-based debug
key registers
key systems
materiel availability issues
Metrics
microprocessor chips
on-chip embedded instrumentation
JTAG interface
pubcrawl
resilience
Resiliency
reverse engineering
Scalability
security
standard test access port
system memory
Cryptography
authorisation
BIT
boundary scan
boundary scan architecture
boundary scan testing
Built-In Test
chip lock
computer debugging
attack surface
debug architectures
depot system repair
embedded systems
firmware
IEEE 1149.1
IEEE standards
joint test action group standards
JTAG
