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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
boundary scan testing
biblio
Mitigating JTAG as an Attack Surface
Submitted by grigby1 on Fri, 08/28/2020 - 10:51am
private instructions
JTAG test access ports
JTAG-based debug
key registers
key systems
materiel availability issues
Metrics
microprocessor chips
on-chip embedded instrumentation
JTAG interface
pubcrawl
resilience
Resiliency
reverse engineering
Scalability
security
standard test access port
system memory
Cryptography
authorisation
BIT
boundary scan
boundary scan architecture
boundary scan testing
Built-In Test
chip lock
computer debugging
attack surface
debug architectures
depot system repair
embedded systems
firmware
IEEE 1149.1
IEEE standards
joint test action group standards
JTAG
biblio
Dynamically obfuscated scan for protecting IPs against scan-based attacks throughout supply chain
Submitted by grigby1 on Tue, 01/23/2018 - 2:21pm
Resiliency
ip protection
Logic gates
noninvasive scan attacks
pattern generation time
Policy
policy-based governance
pubcrawl
Registers
intellectual property
scan-based attacks
scan-based test
Secure Scan
security
Supply Chain
supply chains
Testability
automatic test pattern generation
integrated circuits
integrated circuit testing
integrated circuit test flow
integrated circuit manufacturing
integrated circuit manufacture
integrated circuit design
industrial property
EDA generated scan chains
dynamically-obfuscated scan design
Discrete Fourier transforms
composability
collaboration
Clocks
chip security
boundary scan testing
forum
February Edition of "Embedded Systems Design--Europe" digital magazine is available
Submitted by vbuskirk on Tue, 04/06/2010 - 12:18pm
http://www.embedded.com/europe/
Table of Contents
General Announcements
X-ray
wind power
priority inversion
boundary scan testing
barcode