Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm
Title | Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm |
Publication Type | Journal Article |
Year of Publication | 2014 |
Authors | Bayat-sarmadi, S., Mozaffari-Kermani, M., Reyhani-Masoleh, A. |
Journal | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on |
Volume | 33 |
Pagination | 1105-1109 |
Date Published | July |
ISSN | 0278-0070 |
Keywords | acceptable complexity, Algorithm design and analysis, application specific integrated circuits, Application-specific integrated circuit (ASIC), ASIC analysis, Circuit faults, computational complexity, concurrency control, cryptography, error coverage, error detection, Hardware, hardware overhead reduction, hashing, high performance, high-performance concurrent error detection scheme, injection-based fault simulations, integrity checking, Keccak, low-complexity recomputing, parallel processing, performance overheads, pseudorandom number generation, reliability, robust hardware implementations, rotated operand-based scheme, secure hash algorithm, secure hash algorithm (SHA)-3, security, SHA-3 algorithm, step-forward toward, Transient analysis |
Abstract | The secure hash algorithm (SHA)-3 has been selected in 2012 and will be used to provide security to any application which requires hashing, pseudo-random number generation, and integrity checking. This algorithm has been selected based on various benchmarks such as security, performance, and complexity. In this paper, in order to provide reliable architectures for this algorithm, an efficient concurrent error detection scheme for the selected SHA-3 algorithm, i.e., Keccak, is proposed. To the best of our knowledge, effective countermeasures for potential reliability issues in the hardware implementations of this algorithm have not been presented to date. In proposing the error detection approach, our aim is to have acceptable complexity and performance overheads while maintaining high error coverage. In this regard, we present a low-complexity recomputing with rotated operands-based scheme which is a step-forward toward reducing the hardware overhead of the proposed error detection approach. Moreover, we perform injection-based fault simulations and show that the error coverage of close to 100% is derived. Furthermore, we have designed the proposed scheme and through ASIC analysis, it is shown that acceptable complexity and performance overheads are reached. By utilizing the proposed high-performance concurrent error detection scheme, more reliable and robust hardware implementations for the newly-standardized SHA-3 are realized. |
DOI | 10.1109/TCAD.2014.2307002 |
Citation Key | 6835288 |
- injection-based fault simulations
- Transient analysis
- step-forward toward
- SHA-3 algorithm
- security
- secure hash algorithm (SHA)-3
- secure hash algorithm
- rotated operand-based scheme
- robust hardware implementations
- Reliability
- pseudorandom number generation
- performance overheads
- parallel processing
- low-complexity recomputing
- Keccak
- integrity checking
- acceptable complexity
- high-performance concurrent error detection scheme
- high performance
- hashing
- hardware overhead reduction
- Hardware
- error detection
- error coverage
- Cryptography
- concurrency control
- computational complexity
- Circuit faults
- ASIC analysis
- Application-specific integrated circuit (ASIC)
- application specific integrated circuits
- Algorithm design and analysis