Biblio

Lateral movement attack performs malicious activities by infecting part of a network system first and then moving laterally to the left system in order to compromise more computers. It is widely used in various sophisticated attacks and plays a critical role. This paper aims to quantitatively analyze the transient security and dependability of a critical network system under lateral movement attacks, whose intruding capability increases with the increasing number of attacked computers. We propose a survivability model for capturing the system and adversary behaviors from the time instant of the first intrusion launched from any attacked computer to the other vulnerable computers until defense solution is developed and deployed. Stochastic Reward Nets (SRN) is applied to automatically build and solve the model. The formulas are also derived for calculating the metrics of interest. Simulation is carried out to validate the approximate accuracy of our model and formulas. The quantitative analysis can help network administrators make a trade-off between damage loss and defense cost.

SUMMARY & CONCLUSIONSA Multi-access Edge Computing (MEC) micro data center (MEDC) consists of multiple MEC hosts close to endpoint devices. MEC service is delivered by instantiating a virtualization system (e.g., Virtual Machines or Containers) on a MEC host. MEDC faces more new security risks due to various device connections in an open environment. When more and more IoT/CPS systems are connected to MEDC, it is necessary for MEC service providers to quantitatively analyze any security loss and then make defense-related decision. This paper develops a CTMC model for quantitatively analyzing the security and dependability of a vulnerable MEDC system under lateral movement attacks, from the adversary’s initial successful access until the MEDC becomes resistant to the attack. The proposed model captures the behavior of the system in a scenario where (i) the rate of vulnerable MEC servers being infected increases with the increasing number of infected MEC servers, (ii) each infected MEC server can perform its compromising activity independently and randomly, and (iii) any infected MEC may fail and then cannot provide service. We also introduce the formulas for computing metrics. The proposed model and formula are verified to be approximately accurate by comparing numerical results and simulation results.

Hardware Trojans are malicious modules causing vulnerabilities in designs. Secured hardware designs are desirable in almost all applications. So, it is important to make a trustworthy design that actually exposes malfunctions when a Trojan is present in it. Recently, ring oscillator based detection methods are gaining prominence as they help in detecting Trojans accurately. In this work, a non-destructive method of Trojan detection by modifying the circuit paths into oscillators is proposed. The change in frequencies of ring oscillators upon taking the process corners into account, indicate the presence of Trojans. Since Transient Effect Ring Oscillators (TERO) are also emerging as a good alternative to classical ring oscillators in Trojan detection, an effort is made to analyze the detection capability. Evaluation is done using ISCAS'85 benchmark circuits. Comparison is done in terms of frequency and findings indicate that TERO based Trojan detection is precise. Evaluation is carried out using Xilinx Vivado and ModelSim platforms.

Transient simulation is a critical task of validating the dynamic model of the power grid. We propose an off-line method for validating dynamic grid models and assessing the dynamic security of the grid in the presence of cyberattacks. Simulations are executed in PowerWorld and PSCAD/EMTDC to compare the impact on the grid of cyber-attacks. Generators in the IEEE 14-bus system have been modified to match the need of adjustment in modern power system operation. To get effective measurements for state estimation, SCADA polling model is reproduced in PSCAD/EMTDC by providing controlled sampling frequency. The results of a tripped line case and injecting false data to the loads caused by cyberattacks is presented and analyzed.

The continuous integration of intermittent low-carbon energy resources makes islanded microgrids vulnerable to voltage fluctuations. Besides, different dynamic response of synchronous-based and inverter-based distributed generation (DG) units can result in an instantaneous power imbalance between supply and demand during transients. As a result, the ac-bus voltage of microgrid starts oscillating which might have severe consequences such as blackouts. This paper modifies the conventional control scheme of battery energy storage systems (BESSs) to participate in improving the dynamic behavior of islanded microgrids by mitigating the voltage fluctuations. A piecewise linear-elliptic (PLE) droop is proposed and employed in BESS to achieve an enhanced voltage profile by injecting/absorbing reactive power during transients. In this way, the conventional inverter implemented in BESS turns into a smart inverter to cope with fast transients. Using the proposed approach in this paper, any linear droop curve with a specified coefficient can be replaced by a PLE droop curve. Compared with linear droop, an enhanced dynamic response is achieved by utilizing the proposed PLE droop. Case study results are presented using PSCAD/EMTDC to demonstrate the superiority of the proposed approach in improving the dynamic behavior of islanded microgrids.

The vulnerability of islanded microgrids to voltage and frequency variations is due to the presence of low-inertia distributed generation (DG) units. Besides, the considerable difference between the inertia of synchronous-based and inverter-based DGs results in a power mismatch between generation and consumption during abnormal conditions. As a result, both voltage and frequency of microgrid ac-bus start oscillating which might lead to blackouts. This paper deploys the traditional controller of photovoltaic (PV) units to improve the dynamics of islanded microgrids by reducing the voltage and frequency deviations. To this end, an adaptive piecewise droop (APD) curve is presented and implemented in PV units to attain a faster balance between supply and demand during transients, leading to an enhanced frequency response. Besides, the reactive-power control loop is equipped with a droop characteristic which enables the PV units to inject/absorb reactive power during transients and participate in voltage-profile enhancement of the system. Case study results are presented using PSCAD/EMTDC to confirm the validity of proposed method in improving the dynamic behavior of islanded microgrids.

The behavior of the Current Transformer (CTs) is of utmost importance for protection engineers to ensure reliable operation of power system. CT magnetic saturation is a well-known phenomenon when analyzing its performance characteristics. Nevertheless, transient conditions in the system might be different every time. A good understanding of the magnetic saturation of different CT designs and the effect of saturation on the protection schemes is imperative for developing a robust and dependable protection system. In this paper, various factors that affect CT saturation like X/R ratio, large current magnitudes, DC offset, burden and magnetization remanence are discussed. Analysis of CT saturation based on changes to burden and remanence is performed. In addition to that, the effect of saturation due to these factors on distance protection are presented with test results and analysis. Saturation conditions are analyzed on mho distance elements during phase to ground and three phase faults. Finally, a practical approach to efficiently test the performance of protection schemes under CT saturation conditions is proposed using COMTRADE play back. COMTRADE play back files for various scenarios of CT saturation conditions are generated and used for testing the performance of the protection scheme.

The Transient Public Key Infrastructure or T-PKI is introduced in this paper that allows a transactional approach to attestation, where a Trusted Platform Module (TPM) can stay anonymous to a verifier. In cloud computing and IoT environments, attestation is a critical step in ensuring that the environment is untampered with. With attestation, the verifier would be able to ascertain information about the TPM (such as location, or other system information) that one may not want to disclose. The addition of the Direct Anonymous Attestation added to TPM 2.0 would potentially solve this problem, but it uses the traditional RSA or ECC based methods. In this paper, a Lattice-based approach is used that is both quantum safe, and not dependent on creating a new key pair in order to increase anonymity.

An essential ingredient of the smart grid is software-based services. Increasingly, software is used to support control strategies and services that are critical to the grid's operation. Therefore, its correct operation is essential. For various reasons, software and its configuration needs to be updated. This update process represents a significant overhead for smart grid operators and failures can result in financial losses and grid instabilities. In this paper, we present a framework for determining the root causes of software rollout failures in the smart grid. It uses distributed sensors that indicate potential issues, such as anomalous grid states and cyber-attacks, and a causal inference engine based on a formalism called evidential networks. The aim of the framework is to support an adaptive approach to software rollouts, ensuring that a campaign completes in a timely and secure manner. The framework is evaluated for a software rollout use-case in a low voltage distribution grid. Experimental results indicate it can successfully discriminate between different root causes of failure, supporting an adaptive rollout strategy.

For classical fault analysis, a transient fault is required to be injected during runtime, e.g., only at a specific round. Instead, Persistent Fault Analysis (PFA) introduces a powerful class of fault attacks that allows for a fault to be present throughout the whole execution. One limitation of original PFA as introduced by Zhang et al. at CHES'18 is that the adversary needs know (or brute-force) the faulty values prior to the analysis. While this was addressed at a follow-up work at CHES'20, the solution is only applicable to a single faulty value. Instead, we use the potency of Statistical Fault Analysis (SFA) in the persistent fault setting, presenting Statistical Persistent Fault Analysis (SPFA) as a more general approach of PFA. As a result, any or even a multitude of unknown faults that cause an exploitable bias in the targeted round can be used to recover the cipher's secret key. Indeed, the undesired faults in the other rounds that occur due the persistent nature of the attack converge to a uniform distribution as required by SFA. We verify the effectiveness of our attack against LED and AES.

This paper compares the known method of Analytical Design of Aggregated Regulators (ADAR) with the method of Analytical Design of Optimal Regulators (ADOR). Both equivalence of these methods and the significant difference in the approaches to the analytical synthesis of control laws are shown. It is shown that the ADAR method has significant advantages associated with a simpler and analytical procedure of design of nonlinear laws for optimal control, clear physical representation of weighting factors of optimality criteria, validity and unambiguity of selecting regulator setting parameters, more simple approach to the analysis of the closed-loop system asymptotic stability. These advantages are illustrated by the examples of synthesis.

The determination of the damper cage health is a matter of great importance in those industries that use large synchronous motors in their processes. In the past, unexpected damages of that element implied economic losses amounting up to several million \$. The problem is that, in the technical literature, there is a lack of non-invasive techniques enabling the reliable condition monitoring of this element. This explains the fact that, in industry, rudimentary methods are still employed to determine its condition. This paper proposes the analysis of the stray flux as a way to determine the condition of the damper cage. The paper shows that the analysis of the stray flux under starting yields characteristic time-frequency signatures of the fault components that can be used to reliably determine the condition of the damper. Moreover, the analysis of the stray flux at steady-state operation under asynchronous mode could give useful information to this end. The paper also analyses the influence of the remanent magnetism in the rotor of some synchronous motors, which can make the damper cage diagnosis more difficult; some solutions to this problem are also suggested in the paper.

Since 2018, a broad class of microarchitectural attacks called transient execution attacks (e.g., Spectre and Meltdown) have been disclosed. By abusing speculative execution mechanisms in modern CPUs, these attacks enable adversaries to leak secrets across security boundaries. A transient execution attack typically evolves through multiple stages, termed the attack chain. We find that current transient execution attacks usually rely on static attack chains, resulting in that any blockage in an attack chain may cause the failure of the entire attack. In this paper, we propose a novel defense-aware framework, called TEADS, for synthesizing transient execution attacks dynamically. The main idea of TEADS is that: each attacking stage in a transient execution attack chain can be implemented in several ways, and the implementations used in different attacking stages can be combined together under certain constraints. By constructing an attacking graph representing combination relationships between the implementations and testing available paths in the attacking graph dynamically, we can finally synthesize transient execution attacks which can bypass the imposed defense techniques. Our contributions include: (1) proposing an automated defense-aware framework for synthesizing transient execution attacks, even though possible combinations of defense strategies are enabled; (2) presenting an attacking graph extension algorithm to detect potential attack chains dynamically; (3) implementing TEADS and testing it on several modern CPUs with different protection settings. Experimental results show that TEADS can bypass the defenses equipped, improving the adaptability and durability of transient execution attacks.

With the increasing interdependence of critical infrastructures, the probability of a specific infrastructure to experience a complex cyber-physical attack is increasing. Thus it is important to analyze the risk of an attack and the dynamics of its propagation in order to design and deploy appropriate countermeasures. The attack trees, commonly adopted to this aim, have inherent shortcomings in representing interdependent, concurrent and sequential attacks. To overcome this, the work presented here proposes a stochastic methodology using Petri Nets and Continuous Time Markov Chain (CTMC) to analyze the attacks, considering the individual attack occurrence probabilities and their stochastic propagation times. A procedure to convert a basic attack tree into an equivalent CTMC is presented. The proposed method is applied in a case study to calculate the different attack propagation characteristics. The characteristics are namely, the probability of reaching the root node & sub attack nodes, the mean time to reach the root node and the mean time spent in the sub attack nodes before reaching the root node. Additionally, the method quantifies the effectiveness of specific defenses in reducing the attack risk considering the efficiency of individual defenses.

Recent studies on attacks exploiting processor hardware vulnerabilities have raised significant concern for information security. Particularly, transient execution attacks such as Spectre augment microarchitectural side channels with speculative executions that lead to exfiltration of secretive data not intended to be accessed. Many prior works have demonstrated the manipulation of branch predictors for triggering speculative executions, and thereafter leaking sensitive information through processor microarchitectural components. In this paper, we present a new class of microarchitectural attack, called BranchSpec, that performs information leakage by exploiting state changes of branch predictors in speculative path. Our key observation is that, branch instruction executions in speculative path alter the states of branch pattern history, which are not restored even after the speculatively executed branches are eventually squashed. Unfortunately, this enables adversaries to harness branch predictors as the transmitting medium in transient execution attacks. More importantly, as compared to existing speculative attacks (e.g., Spectre), BranchSpec can take advantage of much simpler code patterns in victim's code base, making the impact of such exploitation potentially even more severe. To demonstrate this security vulnerability, we have implemented two variants of BranchSpec attacks: a side channel where a malicious spy process infers cross-boundary secrets via victim's speculatively executed nested branches, and a covert channel that communicates secrets through intentionally perturbing the branch pattern history structure via speculative branch executions. Our evaluation on Intel Skylake- and Coffee Lake-based processors reveals that these information leakage attacks are highly accurate and successful. To the best of our knowledge, this is the first work to reveal the information leakage threat due to speculative state update in branch predictor. Our studies further broaden the attack surface of processor microarchitecture, and highlight the needs for branch prediction mechanisms that are secure in transient executions.

In transient distributed cloud computing environment, software is vulnerable to attack, which leads to software functional completeness, so it is necessary to carry out functional testing. In order to solve the problem of high overhead and high complexity of unsupervised test methods, an intelligent evaluation method for transient analysis software function testing based on active depth learning algorithm is proposed. Firstly, the active deep learning mathematical model of transient analysis software function test is constructed by using association rule mining method, and the correlation dimension characteristics of software function failure are analyzed. Then the reliability of the software is measured by the spectral density distribution method of software functional completeness. The intelligent evaluation model of transient analysis software function testing is established in the transient distributed cloud computing environment, and the function testing and reliability intelligent evaluation are realized. Finally, the performance of the transient analysis software is verified by the simulation experiment. The results show that the accuracy of the software functional integrity positioning is high and the intelligent evaluation of the transient analysis software function testing has a good self-adaptability by using this method to carry out the function test of the transient analysis software. It ensures the safe and reliable operation of the software.

Large-scale blackouts that have occurred in the past few decades have necessitated the need to do extensive research in the field of grid security assessment. With the aid of synchrophasor technology, which uses phasor measurement unit (PMU) data, dynamic security assessment (DSA) can be performed online. However, existing applications of DSA are challenged by variability in system conditions and unaccounted for measurement errors. To overcome these challenges, this research develops a DSA scheme to provide security prediction in real-time for load profiles of different seasons in presence of realistic errors in the PMU measurements. The major contributions of this paper are: (1) develop a DSA scheme based on PMU data, (2) consider seasonal load profiles, (3) account for varying penetrations of renewable generation, and (4) compare the accuracy of different machine learning (ML) algorithms for DSA with and without erroneous measurements. The performance of this approach is tested on the IEEE-118 bus system. Comparative analysis of the accuracies of the ML algorithms under different operating scenarios highlights the importance of considering realistic errors and variability in system conditions while creating a DSA scheme.

The numerical analysis of transient quantum effects in heterostructure devices with conventional numerical methods tends to pose problems. To overcome these limitations, a novel numerical scheme for the transient non-equilibrium solution of the quantum Liouville equation utilizing a finite volume discretization technique is proposed. Additionally, the solution with regard to the stationary regime, which can serve as a reference solution, is inherently included within the discretization scheme for the transient regime. Resulting in a highly oscillating interference pattern of the statistical density matrix as well in the stationary as in the transient regime, the reflecting nature of the conventional boundary conditions can be an additional source of error. Avoiding these non-physical reflections, the concept of a complex absorbing potential used for the Schrödinger equation is utilized to redefine the drift operator in order to render open boundary conditions for quantum transport equations. Furthermore, the method allows the application of the commonly used concept of inflow boundary conditions.

Transient execution attacks like Spectre, Meltdown and Foreshadow have shown that combinations of microarchitectural side-channels can be synergistically exploited to create side-channel leaks that are greater than the sum of their parts. While both hardware and software mitigations have been proposed against these attacks, provable security has remained elusive. This paper introduces a formal methodology for enabling secure speculative execution on modern processors. We propose a new class of information flow security properties called trace property-dependent observational determinism (TPOD). We use this class to formulate a secure speculation property. Our formulation precisely characterises all transient execution vulnerabilities. We demonstrate its applicability by verifying secure speculation for several illustrative programs.

With the rapid development of the popularity of wireless networks, there are also increasing security threats that follow, and wireless network security issues are becoming increasingly important. Radio frequency fingerprints generated by device tolerance in wireless device transmitters have physical characteristics that are difficult to clone, and can be used for identity authentication of wireless devices. In this paper, we propose a radio frequency fingerprint extraction method based on fractional Fourier transform for transient signals. After getting the features of the signal, we use RPCA to reduce the dimension of the features, and then use KNN to classify them. The results show that when the SNR is 20dB, the recognition rate of this method is close to 100%.

Series-connected IGBTs, when properly controlled, operate similarly to a single device with a much higher voltage capacity. Integrating series IGBTs into a Modular Multilevel Converter (MMC) can reduce its complexity without compromising the voltage capacity. This paper presents the circuit design on the sub-modular level of a MMC in which all the switching devices are series-connected IGBTs. The voltage sharing among the series IGBTs are regulated in a self-balancing manner. Therefore, no central series IGBT controller is needed, which greatly reduces the sensing and communication complexities, increasing the flexibility and expandability. Hardware experiment results demonstrate that the series IGBTs are able to self-regulate the voltage sharing in a fast and accurate manner and the system can operate similarly to a sub-module in a MMC.

Reliability of electronic devices in sub-nanometer technology scale has become a major concern. However, demand for battery operated low power, high performance devices necessitates technology scaling. To meet these contradictory design goals optimization and reliability must be performed simultaneously. This paper proposes by integrating compiler driven transformation and simulated annealing based optimization process for generating optimized low cost transient fault tolerant DSP core. The case study on FIR filter shows improved performance (in terms of reduced area and delay) of proposed approach in comparison to state-of-art transient fault tolerant approach.

Modern processors use branch prediction and speculative execution to maximize performance. For example, if the destination of a branch depends on a memory value that is in the process of being read, CPUs will try to guess the destination and attempt to execute ahead. When the memory value finally arrives, the CPU either discards or commits the speculative computation. Speculative logic is unfaithful in how it executes, can access the victim's memory and registers, and can perform operations with measurable side effects. Spectre attacks involve inducing a victim to speculatively perform operations that would not occur during correct program execution and which leak the victim's confidential information via a side channel to the adversary. This paper describes practical attacks that combine methodology from side channel attacks, fault attacks, and return-oriented programming that can read arbitrary memory from the victim's process. More broadly, the paper shows that speculative execution implementations violate the security assumptions underpinning numerous software security mechanisms, including operating system process separation, containerization, just-in-time (JIT) compilation, and countermeasures to cache timing and side-channel attacks. These attacks represent a serious threat to actual systems since vulnerable speculative execution capabilities are found in microprocessors from Intel, AMD, and ARM that are used in billions of devices. While makeshift processor-specific countermeasures are possible in some cases, sound solutions will require fixes to processor designs as well as updates to instruction set architectures (ISAs) to give hardware architects and software developers a common understanding as to what computation state CPU implementations are (and are not) permitted to leak.

Large scale services have automated hardware remediation to maintain the infrastructure availability at a healthy level. In this paper, we share the current remediation flow at Facebook, and how it is being monitored. We discuss a class of hardware issues that are transient and typically have higher rates during heavy load. We describe how our remediation system was enhanced to be efficient in detecting this class of issues. As hardware and systems change in response to the advancement in technology and scale, we have also utilized machine learning frameworks for hardware remediation to handle the introduction of new hardware failure modes. We present an ML methodology that uses a set of predictive thresholds to monitor remediation efficiency over time. We also deploy a recommendation system based on natural language processing, which is used to recommend repair actions for efficient diagnosis and repair. We also describe current areas of research that will enable us to improve hardware availability further.

This paper presents a sequence switching control (SSC) scheme for buck converters with a series-inductor auxiliary circuit, aiming at improving the load transient response. During an unloading transient, the series inductor is controlled as a small equivalent inductance so as to achieve a fast transient regulation. While in the steady state, the series inductor behaves as a large inductance to reduce the output current ripple. Furthermore, on the basis of the proposed variable inductance circuit, a SSC control scheme is proposed and implemented in a digital form. With the proposed control scheme the unloading transient event is divided into n+1 sub-periods, and in each sub-period, the capacitor-charge balance principle is used to determine the switching time sequence. Furthermore, its feasibility is validated in experiment with a 12V-3.3V low-voltage high-current synchronous buck converter. Experimental results demonstrate that the voltage overshoot of the proposed SSC scheme has improved more than 74% compared to that of the time-optimal control (TOC) scheme.