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Hardware authentication is one of the critical needs in the emerging discipline of design for assurance and design for security. It is concerned with establishing the authenticity and provenance of Integrated Circuits (ICs) reliably and inexpensively at any point in a chip's life-time. Physical unclonable functions (PUFs) have significant promise as basic primitives for authentication since they can serve as intrinsically-generated hardware roots-of-trust within specific authentication protocols. PUFs are pseudo-random functions that exploit the randomness inherent in the IC manufacturing to generate random output strings.
The central challenge in realizing the potential of strong PUFs is their vulnerability to model-building attacks using machine learning (ML) methodologies. Despite the effort devoted to PUFs over the past decade, there is still a lack of a strong silicon PUF that is both reliable and ML-resilient. This project develops a strong PUF that exploits the physics of nanometer-scale CMOS to attain security properties that are superior to existing designs. This new PUF exploits the physics of scaled transistors, namely subthreshold operation and drain-induced barrier lowering, to realize continuous nonlinearity. The project also investigates effective algorithmic techniques, based on novel codes and lattice-constructions, to enhance the overall structure as well as the robustness of the resulting PUF output to enable high-capacity secret key generation. The strong PUFs developed in this project possess a very large input-output space, making them invaluable to many potential security applications.
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SaTC: STARSS: Hardware Authentication through High-Capacity PUF-Based Secret Key Generation and Lattice Coding