Physical side channels pose a big threat to the security of embedded hardware. The differential power analysis (DPA) attack is a well known side channel threat which exploits the linear dependence of the power on the secret data or an intermediate value correlated to the secret data through statistical model building. This project addresses the DPA vulnerability by deploying a technology cell library consisting of private gates. The technique developed will make embedded hardware less vulnerable to side-channel attacks, thereby securing private user data and transactions. This project develops logic level and netlist level metrics to model the DPA vulnerability of a circuit. The logic level metric, called normalized variance, is efficiently computed for a logic network with switching probability and switched capacitance estimation through BDDs or other methods. The project develops a more accurate but computationally more expensive metric, which is a refinement of the normalized variance and is deployed at circuit level.
SaTC: STARSS: Metric & CAD for DPA Resistance