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Truly ubiquitous computing with very small, self-powered and wirelessly networked integrated circuits will become possible within a decade. Applications of these devices include biosensors, environmental monitors, and defense, all of which bring a need for security and privacy. Enabling the use of strong cryptographic algorithms on extremely constrained devices requires rethinking, from an energy-first perspective, the design and implementation of basic cryptographic building blocks. The Secure Dust project seeks to reduce the energy of cryptographic functions in advanced technologies by an order of magnitude, and to validate the designs using test chips. The findings of this project will help to secure future ubiquitous devices and the Internet of Things.
The specific research objective of this project is to explore the scaling down of security functions into advanced CMOS technologies and in particular the important role of manufacturing variations and noise that can be both advantageous (Physical Unclonable Functions and Random Number Generation) and detrimental (side-channel resistant ciphers and hash functions) depending on the cryptography block. We target an energy budget of picojoules per secure transaction, built upon basic cryptography functions. The project combines design expertise in lightweight cryptography using block ciphers, hash functions, PUFs and RNGs, along with low-energy techniques and realistic semiconductor design flows and economic realities. FPGA-prototyping and CMOS FinFET test chips will be used to demonstrate complete cryptosystem functionality, including side-channel susceptibility.
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STARSS: Small: SecureDust - The Physical Limits of Information Security