Biblio

Security evaluation of third-party cryptographic Soft/Hard IP (Intellectual Property) core is often ignored due to several reasons including, lack of awareness about its adversity, lack of knowledge about validation methodology or considering security as a byproduct. Particularly, the security validation of bought-out Hardware IP core is important before being deployed in particle means. In this paper, we present Look-Up-Table (LUT) based unrolled implementation of low latency cipher, PRINCE as an hard IP core and show how the susceptible implementation (nested and flexible placement of IP cores) can be experimentally exploited to reveal secret key in FPGA using power analysis attack. Such vulnerability in constrained devices, Internet-of-Things(IoT), causes serious threats in cyber physical system.

Diffie-Hellman and RSA encryption/decryption involve computationally intensive cryptographic operations such as modular exponentiation. Computing modular exponentiation using appropriate pre-computed pairs of bases and exponents was first proposed by Boyko et al. In this paper, we present a reconfigurable architecture for pre-computation methods to compute modular exponentiation and thereby speeding up RSA and Diffie-Hellman like protocols. We choose Diffie-Hellman key pair (a, ga mod p) to illustrate the efficiency of Boyko et al's scheme in hardware architecture that stores pre-computed values ai and corresponding gai in individual block RAM. We use a Pseudo-random number generator (PRNG) to randomly choose ai values that are added and corresponding gai values are multiplied using modular multiplier to arrive at a new pair (a, ga mod p). Further, we present the advantage of using Montgomery and interleaved methods for batch multiplication to optimise time and area. We show that a 1024-bit modular exponentiation can be performed in less than 73$μ$s at a clock rate of 200MHz on a Xilinx Virtex 7 FPGA.