Biblio

Security evaluation of third-party cryptographic Soft/Hard IP (Intellectual Property) core is often ignored due to several reasons including, lack of awareness about its adversity, lack of knowledge about validation methodology or considering security as a byproduct. Particularly, the security validation of bought-out Hardware IP core is important before being deployed in particle means. In this paper, we present Look-Up-Table (LUT) based unrolled implementation of low latency cipher, PRINCE as an hard IP core and show how the susceptible implementation (nested and flexible placement of IP cores) can be experimentally exploited to reveal secret key in FPGA using power analysis attack. Such vulnerability in constrained devices, Internet-of-Things(IoT), causes serious threats in cyber physical system.