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2021-08-03
Ragchaa, Byambajav, Wu, Liji, Zhang, Xiangmin, Chu, Honghao.  2020.  A Multi-Channel 12 bit, 100Ksps 0.35um CMOS ADC IP core for Security SoC. 2020 IEEE 15th International Conference on Solid-State Integrated Circuit Technology (ICSICT). :1—3.
This paper presents a multi-channel, 12 bit, ADC IP core with programmable gain amplifier which is implemented as part of novel Security SoC. The measurement results show that effective number of bits (ENOB) of the ADC IP core reaches 8 bits, SNDR of 47.14dB and SFDR of 56.55dB at 100Ksps sampling rate. The input voltage range is 0V to 3.3V, active die area of 700um*620um in 0.35um CMOS process, and the ADC consumes 22mW in all channel auto-scan mode at 3.3V power supply.