Biblio

With the emergence and development of quantum computers, the traditional public-key cryptography (PKC) is facing the risk of being cracked. In order to resist quantum attacks and ensure long-term communication security, NIST launched a global collection of Post Quantum Cryptography (PQC) standards in 2016, and it is currently in the third round of selection. There are three Lattice-based PKC algorithms that stand out, and NTRU is one of them. In this article, we proposed the first complete and compact full hardware implementation of NTRU algorithm submitted in the third round. By using one structure to complete the design of the three types of complex polynomial multiplications in the algorithm, we achieved better performance while reducing area costs.

This paper presents a multi-channel, 12 bit, ADC IP core with programmable gain amplifier which is implemented as part of novel Security SoC. The measurement results show that effective number of bits (ENOB) of the ADC IP core reaches 8 bits, SNDR of 47.14dB and SFDR of 56.55dB at 100Ksps sampling rate. The input voltage range is 0V to 3.3V, active die area of 700um*620um in 0.35um CMOS process, and the ADC consumes 22mW in all channel auto-scan mode at 3.3V power supply.

Profiled DPA is a new method combined with machine learning method in side channel attack which is put forward by Whitnall in CHES 2015.[1]The most important part lies in effectiveness of extracting information. This paper introduces a new rule Explained Local Variance (ELV) to extract information in profiled stage for profiled DPA. It attracts information effectively and shields noise to get better accuracy than the original rule. The ELV enables an attacker to use less power traces to get the same result as before. It also leads to 94.6% space reduction and 29.2% time reduction for calculation. For security circuit implementation, a high order masking scheme in modelsim is implemented. A new exchange network is put forward. 96.9% hardware resource is saved due to the usage of this network.

With the application of integrated circuits (ICs) appears in all aspects of life, whether an IC is security and reliable has caused increasing worry which is of significant necessity. An attacker can achieve the malicious purpose by adding or removing some modules, so called hardware Trojans (HTs). In this paper, we use side-channel analysis (SCA) and support vector machine (SVM) classifier to determine whether there is a Trojan in the circuit. We use SAKURA-G circuit board with Xilinx SPARTAN-6 to complete our experiment. Results show that the Trojan detection rate is up to 93% and the classification accuracy is up to 91.8475%.

This paper presents some verifications and improved considerations of NAND PUF, which was introduced recently [1]. For embedded system such as IC cards, the secret data in memory is vulnerable, so it has to be encrypted and secured. PUF circuit is sensitive to environmental condition, especially in the temperature range influences and variations of current and voltages. This proposed bank IC card would be operated in AB class standard, i.e. voltage would be constant except for power mode changing. Nevertheless, operational temperatures may vary such as the situation of outdoor ATM. Thus, this paper presented some results of our PUF work in Cadence, also on FPGA board. Around 5ns is spent for stabilization of our PUF output that is under variance temperature when power mode changes. Inter Hamming distances is 48.9%, very near to uniqueness and robustness value, that our PUF is feasible to use in bankcard. The maximum error rates are HDintra(0$^\circ$C) = 3.9961 and HDintra(80$^\circ$C) = 3.9916 where at antipoles, while the minimum error rate is HDintra(20$^\circ$C) = 2.9 at room temperature. For improvement, Repetition, LDPC and SEC-DED codes are considered that would eliminate error rates.