Visible to the public Biblio

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2020-02-26
Shi, Qihang, Vashistha, Nidish, Lu, Hangwei, Shen, Haoting, Tehranipoor, Bahar, Woodard, Damon L, Asadizanjani, Navid.  2019.  Golden Gates: A New Hybrid Approach for Rapid Hardware Trojan Detection Using Testing and Imaging. 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). :61–71.

Hardware Trojans are malicious modifications on integrated circuits (IC), which pose a grave threat to the security of modern military and commercial systems. Existing methods of detecting hardware Trojans are plagued by the inability of detecting all Trojans, reliance on golden chip that might not be available, high time cost, and low accuracy. In this paper, we present Golden Gates, a novel detection method designed to achieve a comparable level of accuracy to full reverse engineering, yet paying only a fraction of its cost in time. The proposed method inserts golden gate circuits (GGC) to achieve superlative accuracy in the classification of all existing gate footprints using rapid scanning electron microscopy (SEM) and backside ultra thinning. Possible attacks against GGC as well as malicious modifications on interconnect layers are discussed and addressed with secure built-in exhaustive test infrastructure. Evaluation with real SEM images demonstrate high classification accuracy and resistance to attacks of the proposed technique.

2018-05-02
Shi, Qihang, Xiao, Kan, Forte, Domenic, Tehranipoor, Mark M..  2017.  Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-Authentication. Proceedings of the on Great Lakes Symposium on VLSI 2017. :339–344.
Hardware Trojan insertion and intellectual property (IP) theft are two major concerns when dealing with untrusted foundries. Most existing mitigation techniques are limited in protecting against both vulnerabilities. Split manufacturing is designed to stop IP piracy and IC cloning, but it fails at preventing untargeted hardware Trojan insertion and incurs significant overheads when high level of security is demanded. Built-in self-authentication (BISA) is a low cost technique for preventing and detecting hardware Trojan insertion, but is vulnerable to IP piracy, IC cloning or redesign attacks, especially on original circuitry. In this paper, we propose an obfuscated built-in self-authentication (OBISA) technique that combines and optimizes both technique so that they complement and improve security against both vulnerabilities. Performance of the proposed OBISA technique is presented with experimental implementation on same benchmark circuits as used in the existing wire lifting technique. The security performance is evaluated with the most popular split manufacturing security metrics.
2017-05-17
Guin, Ujjwal, Shi, Qihang, Forte, Domenic, Tehranipoor, Mark M..  2016.  FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs. ACM Trans. Des. Autom. Electron. Syst.. 21:63:1–63:20.

With the advent of globalization in the semiconductor industry, it is necessary to prevent unauthorized usage of third-party IPs (3PIPs), cloning and unwanted modification of 3PIPs, and unauthorized production of ICs. Due to the increasing complexity of ICs, system-on-chip (SoC) designers use various 3PIPs in their design to reduce time-to-market and development costs, which creates a trust issue between the SoC designer and the IP owners. In addition, as the ICs are fabricated around the globe, the SoC designers give fabrication contracts to offshore foundries to manufacture ICs and have little control over the fabrication process, including the total number of chips fabricated. Similarly, the 3PIP owners lack control over the number of fabricated chips and/or the usage of their IPs in an SoC. Existing research only partially addresses the problems of IP piracy and IC overproduction, and to the best of our knowledge, there is no work that considers IP overuse. In this article, we present a comprehensive solution for preventing IP piracy and IC overproduction by assuring forward trust between all entities involved in the SoC design and fabrication process. We propose a novel design flow to prevent IC overproduction and IP overuse. We use an existing logic encryption technique to obfuscate the netlist of an SoC or a 3PIP and propose a modification to enable manufacturing tests before the activation of chips which is absolutely necessary to prevent overproduction. We have used asymmetric and symmetric key encryption, in a fashion similar to Pretty Good Privacy (PGP), to transfer keys from the SoC designer or 3PIP owners to the chips. In addition, we also propose to attach an IP digest (a cryptographic hash of the entire IP) to the header of an IP to prevent modification of the IP by the SoC designers. We have shown that our approach is resistant to various attacks with the cost of minimal area overhead.