| Title | ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories |
| Publication Type | Conference Paper |
| Year of Publication | 2017 |
| Authors | Rakshit, Joydeep, Mohanram, Kartik |
| Conference Name | Proceedings of the 54th Annual Design Automation Conference 2017 |
| Publisher | ACM |
| Conference Location | New York, NY, USA |
| ISBN Number | 978-1-4503-4927-7 |
| Keywords | authentication, Human Behavior, Merkle Tree, Metrics, non-volatile memories, pubcrawl, Scalability, Tamper resistance |
| Abstract | Data tampering threatens data integrity in emerging non-volatile memories (NVMs). Whereas Merkle Tree (MT) memory authentication is effective in thwarting data tampering attacks, it drastically increases cell writes and memory accesses, adversely impacting NVM energy, lifetime, and system performance (instructions per cycle (IPC)). We propose ASSURE, a low overhead, high performance Authentication Scheme for SecURE energy efficient (ASSURE) NVMs. ASSURE synergistically integrates (i) smart message authentication codes (SMACs), which eliminate redundant cell writes by enabling MAC computation of only modified words on memory writes, with (ii) multi-root MTs (MMTs), which reduce MT reads/writes by constructing either high performance static MMTs (SMMTs) or low overhead dynamic MMTs (DMMTs) over frequently accessed memory regions. Our full-system simulations of the SPEC CPU2006 benchmarks on a triple-level cell (TLC) resistive RAM (RRAM) architecture show that on average, SMMT ASSURE (DMMT ASSURE) reduces NVM energy by 59% (55%), increases memory lifetime by 2.36x (2.11x), and improves IPC by 11% (10%), over state-of-the-art MT memory authentication. |
| URL | http://doi.acm.org/10.1145/3061639.3062205 |
| DOI | 10.1145/3061639.3062205 |
| Citation Key | rakshit_assure:_2017 |
ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories