A Scalable and Reconfigurable Verification and Benchmark Environment for Network on Chip Architecture
Title | A Scalable and Reconfigurable Verification and Benchmark Environment for Network on Chip Architecture |
Publication Type | Conference Paper |
Year of Publication | 2017 |
Authors | Lokananta, F., Hartono, D., Tang, C. M. |
Conference Name | 2017 4th International Conference on New Media Studies (CONMEDIA) |
Keywords | benchmark, benchmark environment, Benchmark testing, complex on-chip communication problems, compositionality, Generators, integrated circuit design, interconnection architectures, Metrics, Monitoring, network-on-chip, network-on-chip architecture, NoC, Object oriented modeling, on-chip component, pubcrawl, reconfigurable verification, resilience, Resiliency, reusable methodology, Scalability, scalable verification, standardized methodology, system-on-chip, Throughput, Traffic Control, Universal Verification Methodology, UVM, verification |
Abstract | To reduce the complex communication problem that arise as the number of on-chip component increases, the use of Network-on-Chip (NoC) as interconnection architectures have become more promising to solve complex on-chip communication problems. However, providing a suitable test base to measure and verify functionality of any NoC is a compulsory. Universal Verification Methodology (UVM) is introduced as a standardized and reusable methodology for verifying integrated circuit design. In this research, a scalable and reconfigurable verification and benchmark environment for NoC is proposed. |
URL | https://ieeexplore.ieee.org/document/8266022 |
DOI | 10.1109/CONMEDIA.2017.8266022 |
Citation Key | lokananta_scalable_2017 |
- on-chip component
- verification
- UVM
- Universal Verification Methodology
- traffic control
- Throughput
- system-on-chip
- standardized methodology
- scalable verification
- Scalability
- reusable methodology
- Resiliency
- resilience
- reconfigurable verification
- pubcrawl
- benchmark
- Object oriented modeling
- NoC
- network-on-chip architecture
- network-on-chip
- Monitoring
- Metrics
- interconnection architectures
- integrated circuit design
- Generators
- Compositionality
- complex on-chip communication problems
- Benchmark testing
- benchmark environment