Visible to the public A Scalable and Reconfigurable Verification and Benchmark Environment for Network on Chip Architecture

TitleA Scalable and Reconfigurable Verification and Benchmark Environment for Network on Chip Architecture
Publication TypeConference Paper
Year of Publication2017
AuthorsLokananta, F., Hartono, D., Tang, C. M.
Conference Name2017 4th International Conference on New Media Studies (CONMEDIA)
Keywordsbenchmark, benchmark environment, Benchmark testing, complex on-chip communication problems, compositionality, Generators, integrated circuit design, interconnection architectures, Metrics, Monitoring, network-on-chip, network-on-chip architecture, NoC, Object oriented modeling, on-chip component, pubcrawl, reconfigurable verification, resilience, Resiliency, reusable methodology, Scalability, scalable verification, standardized methodology, system-on-chip, Throughput, Traffic Control, Universal Verification Methodology, UVM, verification
Abstract

To reduce the complex communication problem that arise as the number of on-chip component increases, the use of Network-on-Chip (NoC) as interconnection architectures have become more promising to solve complex on-chip communication problems. However, providing a suitable test base to measure and verify functionality of any NoC is a compulsory. Universal Verification Methodology (UVM) is introduced as a standardized and reusable methodology for verifying integrated circuit design. In this research, a scalable and reconfigurable verification and benchmark environment for NoC is proposed.

URLhttps://ieeexplore.ieee.org/document/8266022
DOI10.1109/CONMEDIA.2017.8266022
Citation Keylokananta_scalable_2017