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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
UVM
biblio
Architecture Analysis and Verification of I3C Protocol
Submitted by grigby1 on Tue, 11/12/2019 - 3:29pm
SoC
MIPI
Monitoring
Pins
policy-based governance
privacy
protocol verification
Protocols
pubcrawl
IP networks
system Verilog
test environments
Universal Verification Methodology
UVM
verification components
verification environment
VLSI
formal verification
back end design
base class library
Clocks
collaboration
composability
Compositionality
Conferences
digital integrated circuits
Aerospace electronics
front end design
hardware description languages
I3C
I3C bus protocol
improved inter integrated circuit
integrated circuit design
integrated circuit testing
biblio
Design of Generic Verification Procedure for IIC Protocol in UVM
Submitted by grigby1 on Tue, 11/12/2019 - 3:29pm
SDA(Serial data line)
Monitoring
policy-based governance
privacy
product development
program verification
protocol verification
Protocols
pubcrawl
SCL(Serial clock line)
Mentor graphic Questasim 10.4e
standard method
Synchronization
Universal Verification Methodology
UVC(Universal verification component)
UVM
UVM(Univeral verification methodology)
Verilog
Vivado
field buses
APB(Advanced peripheral bus)
bugs
Clocks
code coverage
collaboration
composability
Compositionality
Conferences
DUT(Design under test)
Aerospace electronics
functional coverage
generic verification procedure
hardware description languages
Hardware design languages
IIC bus protocol
IIC controller
IIC protocol
Libraries
biblio
Robust Functional Verification Framework Based in UVM Applied to an AES Encryption Module
Submitted by grigby1 on Fri, 06/28/2019 - 9:36am
Measurement
Verification Framework
UVM
Universal Verification Methodology
System Verilog-based functional verification
standards
scalable verification
Scalability
robust functional verification framework
Resiliency
resilience
Reliability engineering
pubcrawl
Metrics
AES encryption module
information-security applications
Industries
high-level designs
hardware description languages
functional verification
formal verification
encryption
direct verification methodologies
digital design industry
design requirements
Cryptography
Compositionality
biblio
A Scalable and Reconfigurable Verification and Benchmark Environment for Network on Chip Architecture
Submitted by grigby1 on Wed, 05/09/2018 - 1:47pm
on-chip component
verification
UVM
Universal Verification Methodology
traffic control
Throughput
system-on-chip
standardized methodology
scalable verification
Scalability
reusable methodology
Resiliency
resilience
reconfigurable verification
pubcrawl
benchmark
Object oriented modeling
NoC
network-on-chip architecture
network-on-chip
Monitoring
Metrics
interconnection architectures
integrated circuit design
Generators
Compositionality
complex on-chip communication problems
Benchmark testing
benchmark environment
