| Title | Security Network On-Chip for Mitigating Side-Channel Attacks |
| Publication Type | Conference Paper |
| Year of Publication | 2019 |
| Authors | Kenarangi, Farid, Partin-Vaisband, Inna |
| Conference Name | 2019 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP) |
| Keywords | active attack, advance invasive attacks, advance noninvasive attacks, advanced technology nodes, attack detection, attack-specific countermeasures, compromised device, contemporary hardware threats, Data analysis, design complexity, electromagnetic analysis attacks, electromagnetic interference, hardware security, hardware security threats, high-confidence security network on-chip, individual threats, integrated circuit design, integrated circuits, learning (artificial intelligence), machine learning, machine learning security IC, malicious activity, malicious physical interference, Metrics, modern ICs, multiple countermeasures, network on chip security, network-on-chip, on-chip distribution networks, On-chip power delivery, on-chip voltage variations, operating device-under-attack, physical interaction, pubcrawl, Resiliency, robust confidence security network on-chip, Scalability, security networks, security of data, Sensors, Side-channel attack, side-channel attack mitigation, side-channel attacks, strict performance requirements, system security, system-on-chip, Timing, trained ML ICs |
| Abstract | Hardware security is a critical concern in design and fabrication of integrated circuits (ICs). Contemporary hardware threats comprise tens of advance invasive and non-invasive attacks for compromising security of modern ICs. Numerous attack-specific countermeasures against the individual threats have been proposed, trading power, area, speed, and design complexity of a system for security. These typical overheads combined with strict performance requirements in advanced technology nodes and high complexity of modern ICs often make the codesign of multiple countermeasures impractical. In this paper, on-chip distribution networks are exploited for detecting those hardware security threats that require non-invasive, yet physical interaction with an operating device-under-attack (e.g., measuring equipment for collecting sensitive information in side-channel attacks). With the proposed approach, the effect of the malicious physical interference with the device-under-attack is captured in the form of on-chip voltage variations and utilized for detecting malicious activity in the compromised device. A machine learning (ML) security IC is trained to predict system security based on sensed variations of signals within on-chip distribution networks. The trained ML ICs are distributed on-chip, yielding a robust and high-confidence security network on-chip. To halt an active attack, a variety of desired counteractions can be executed in a cost-effective manner upon the attack detection. The applicability and effectiveness of these security networks is demonstrated in this paper with respect to power, timing, and electromagnetic analysis attacks. |
| DOI | 10.1109/SLIP.2019.8771328 |
| Citation Key | kenarangi_security_2019 |
Security Network On-Chip for Mitigating Side-Channel Attacks