| Title | Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array |
| Publication Type | Conference Paper |
| Year of Publication | 2021 |
| Authors | Kadlubowski, Lukasz A., Kmon, Piotr |
| Conference Name | 2021 24th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS) |
| Keywords | Buildings, compositionality, Metrics, Monte Carlo methods, Object oriented modeling, object oriented programming, object-oriented programming, pixel radiation detectors, pubcrawl, Radiation detectors, resilience, Resiliency, Scalability, scalable verification, SystemVerilog, Time measurement, time-to-digital converter, Vernier |
| Abstract | The goal of building a system for precise time measurement in pixel radiation detectors motivates the development of flexible design and verification environment. It should be suitable for quick simulations when individual elements of the system are developed and should be scalable so that systemlevel verification is possible as well. The approach presented in this paper is to utilize the power of SystemVerilog language and apply basic Object-Oriented Programming concepts to the test program. Since the design under test is a full-custom mixed-signal design, it must be simulated with AMS simulator and various features of analog design environment are used as well (Monte Carlo analysis, corner analysis, schematic capture GUI-related functions). The presented approach combines these two worlds and should be suitable for small academia projects, where design and verification is seldom done by separate teams. |
| DOI | 10.1109/DDECS52668.2021.9417054 |
| Citation Key | kadlubowski_test_2021 |
Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array