| Title | Error Detection And Correction In TCAMS Based SRAM |
| Publication Type | Conference Paper |
| Year of Publication | 2021 |
| Authors | Mishra, Suman, Radhika, K, Babu, Y.Murali Mohan |
| Conference Name | 2021 6th International Conference on Signal Processing, Computing and Control (ISPCC) |
| Keywords | composability, error correction, error detection, forward error correction, FPGA, Market research, Memory management, Metrics, Production, pubcrawl, Random access memory, Redundancy, Resiliency, security, Signal processing, SRAM |
| Abstract | Ternary content addressable memories (TCAMs) widely utilized in network systems to enforce the labeling of packets. For example, they are used for packet forwarding, security, and software-defined networks (SDNs). TCAMs are typically deployed as standalone instruments or as an embedded intellectual property component on application-specific integrated circuits. However, field-programmable gate arrays (FPGAs) do not have TCAM bases. However, FPGAs' versatility allows them to appeal for SDN deployment, and most FPGA vendors have SDN production kits. Those need to help TCAM features and then simulate TCAMs using the FPGA logic blocks. Several methods to reproduction TCAMs on FPGAs have been introduced in recent years. Some of them use a huge multiple storage blocks within modern FPGAs to incorporate TCAMs. A trouble while remembrances are that soft errors that corrupt stored bits can affect them. Memories may be covered by a parity test to identify errors or by an error correction code, although this involves extra bits in a word frame. This brief considers memory security used to simulate TCAMs. It is shown in particular that by leveraging the assumption its part of potential memory information is true, most single-bit errors can be resolved when memoirs are emulated with a parity bit. |
| DOI | 10.1109/ISPCC53510.2021.9609517 |
| Citation Key | mishra_error_2021 |
Error Detection And Correction In TCAMS Based SRAM