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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
hardware parallelism
biblio
A high speed implementation counter mode cryptography using hardware parallelism
Submitted by grigby1 on Thu, 04/20/2017 - 12:41pm
parallel computing
hardware parallelism
Heracles toolkit
high speed implementation counter mode cryptography
network-on-chip
network on chip
Network on Chip(NoC)
network on chip security
NoC
graphics processing units
pubcrawl
Resiliency
Scalability
secure data transmission
security mechanisms
Software algorithms
unsecured networks
DES
Big Data
composability
Counter Mode Cryptography (CTR)
CPU
Cryptography
CTR
data encryption standard core
Data Encryption Standard (DES)
Algorithm design and analysis
encryption
field programmable gate arrays
FPGA
FPGA board
gpu
Grafic Process Unite(GPU)
graphics processing unit
biblio
Scalable Packet Classification for Datacenter Networks
Submitted by BrandonB on Wed, 05/06/2015 - 11:58am
IP networks
VLANs
VLAN
virtual machines
telecommunication network routing
storage penalty
Software
Scalability
router architectures
packet forwarding
packet classification
Local area networks
length combinations
classification rules
Indexes
hash table
hardware parallelism
Hardware
firewalls
encoding
encoded rule expansion
Decision trees
datacenter networks
datacenter network
data structures
computer centres
