Skip to Main Content Area
CPS-VO
Contact Support
Browse
Calendar
Announcements
Repositories
Groups
Search
Search for Content
Search for a Group
Search for People
Search for a Project
Tagcloud
› Go to login screen
Not a member?
Click here to register!
Forgot username or password?
Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
CTR
biblio
A high speed implementation counter mode cryptography using hardware parallelism
Submitted by grigby1 on Thu, 04/20/2017 - 12:41pm
parallel computing
hardware parallelism
Heracles toolkit
high speed implementation counter mode cryptography
network-on-chip
network on chip
Network on Chip(NoC)
network on chip security
NoC
graphics processing units
pubcrawl
Resiliency
Scalability
secure data transmission
security mechanisms
Software algorithms
unsecured networks
DES
Big Data
composability
Counter Mode Cryptography (CTR)
CPU
Cryptography
CTR
data encryption standard core
Data Encryption Standard (DES)
Algorithm design and analysis
encryption
field programmable gate arrays
FPGA
FPGA board
gpu
Grafic Process Unite(GPU)
graphics processing unit
