| Title | A high speed implementation counter mode cryptography using hardware parallelism |
| Publication Type | Conference Paper |
| Year of Publication | 2016 |
| Authors | Najjar-Ghabel, S., Yousefi, S., Lighvan, M. Z. |
| Conference Name | 2016 Eighth International Conference on Information and Knowledge Technology (IKT) |
| Date Published | sep |
| Keywords | Algorithm design and analysis, Big Data, composability, Counter Mode Cryptography (CTR), CPU, cryptography, CTR, Data Encryption Standard (DES), data encryption standard core, DES, Encryption, field programmable gate arrays, FPGA, FPGA board, GPU, Grafic Process Unite(GPU), graphics processing unit, graphics processing units, hardware parallelism, Heracles toolkit, high speed implementation counter mode cryptography, network on chip, network on chip security, Network on Chip(NoC), network-on-chip, NoC, parallel computing, pubcrawl, Resiliency, Scalability, secure data transmission, security mechanisms, Software algorithms, unsecured networks |
| Abstract | Nowadays, cryptography is one of the common security mechanisms. Cryptography algorithms are used to make secure data transmission over unsecured networks. Vital applications are required to techniques that encrypt/decrypt big data at the appropriate time, because the data should be encrypted/decrypted are variable size and usually the size of them is large. In this paper, for the mentioned requirements, the counter mode cryptography (CTR) algorithm with Data Encryption Standard (DES) core is paralleled by using Graphics Processing Unit (GPU). A secondary part of our work, this parallel CTR algorithm is applied on special network on chip (NoC) architecture that designed by Heracles toolkit. The results of numerical comparison show that GPU-based implementation can be achieved better runtime in comparison to the CPU-based one. Furthermore, our final implementations show that parallel CTR mode cryptography is achieved better runtime by using special NoC that applied on FPGA board in comparison to GPU-based and CPU ones. |
| DOI | 10.1109/IKT.2016.7777787 |
| Citation Key | najjar-ghabel_high_2016 |
A high speed implementation counter mode cryptography using hardware parallelism