Division of Computer and Network Systems (CNS)

Worms have emerged as one of the leading threats to our information systems and critical infrastructures. Despite the tremendous research effort in combating worms, new computer and system vulnerabilities are continuously reported and new worm attacks keep succeeding. Another significant trend in worm attacks is that the number of worm attacks against emergent networks, such as P2P networks, cellphone networks, and sensor networks, is rapidly growing.

This project is developing an automated defense system for enterprise networks against malicious code attacks such as worms, viruses and spyware. This system responds to attacks by dynamically and selectively quarantining hosts, services, and other networked devices. Traditional containment systems based on firewalls and individual host isolation are not adequate for containing the new generation of local-scanning, topological, metaserver and contagion worms that can spread very quickly through an enterprise.

The combination of widespread software homogeneity and the Internet's unrestricted communication model creates an ideal climate for infectious, self-propagating pathogens - "worms" and "viruses" - with each new generation of outbreaks demonstrating increasing speed, virulence, and sophistication. The Center for Internet Epidemiology and Defenses aims to address twin fundamental needs: to better understand the behavior and limitations of Internet epidemics, and to develop systems that can automatically defend against new outbreaks in real-time.

While some researchers have aimed at efficiency, they have often developed algorithms without proving them secure. Conversely, researchers focussed on provable security have often produced impractical algorithms. Providing both performance and provable security entails great effort in each domain, often entailing a strange marriage of mathematics with implementation considerations.

Electronic System Level ( ESL ) designs , specified behaviorally using high-level languages such as SystemC , raise the level of hardware design abstraction . This approach crucially depends on behavioral synthesis , which compiles ESL designs to Register Transfer Level ( RTL ) designs . However , optimizations performed by synthesis tools make their implementation error-prone , undermining the trustworthiness of synthesized hardware. This research develops a mechanized infrastructure for certifying hardware designs generated by behavioral synthesis .