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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
precalculated LUT
biblio
FPGA based hardware implementation of AES Rijndael algorithm for Encryption and Decryption
Submitted by grigby1 on Thu, 04/20/2017 - 12:40pm
secure data transmission
Inverse S-Box transformations
network on chip
network on chip security
network security algorithm
pre-calculated look-up tables
precalculated LUT
pubcrawl
Resiliency
Rijndael
Scalability
inverse mix-columns transformations
Table lookup
timing
Verilog-HDL
Virtex-7 XC7VX690T chip
wired digital communication networks
wireless digital communication networks
Xilinx ISE Design Suite-14.7 Tool
Xilinx Virtex-7 FPGA
Xilinx XPower Analyzer
decryption
AES-128
AES-192
AES-256
AES Rijndael algorithm
Algorithm design and analysis
algorithmic functions
Clocks
composability
Cryptography
advanced encryption standard (AES)
encryption
Field Programmable Gate Array (FPGA)
field programmable gate arrays
FPGA based hardware implementation
Galois field multiplications
Galois fields
GF (28)
Hardware Description Language (HDL)
hardware description languages
