hardware description languages

biblio

A Support Vector Machine Algorithm for PIR Special Processor

Submitted by aekwall on Mon, 12/14/2020 - 11:30am

data processing algorithm
timing design
SVM classification
real-time intellectual property core
pyroelectric infrared sensor
pyroelectric detectors
PIR special processor
PIR sensor
mathematical statistics
infrared products
human motion detection technology
function design
fast Fourier transform
distance 15.0 m
Support vector machines
continuous improvement
algorithm flow
IP core
hardware description languages
Kalman filters
Predictive Metrics
data acquisition
industrial property
microcontrollers
composability
pubcrawl
Resiliency
support vector machine

biblio

QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment

Submitted by grigby1 on Fri, 09/18/2020 - 1:15pm

pre-silicon security assessment
design stage
formal verification methods
hardware designer
hardware overhead
hardware system
hardware vulnerabilities
language based framework
language-based approach
language-based hardware security verification
malicious logic detection
potential security vulnerabilities
design mistakes
promising solution
QIF model
QIF-Verilog
quantified information flow model
quantitative information-flow
security rules
verification process
Verilog type systems
vulnerable logic detection
compiler security
integrated circuit testing
Hardware design languages
Cryptography
security solutions
security of data
security
pubcrawl
Metrics
resilience
Resiliency
Hardware
Integrated circuit modeling
hardware description languages
Scalability
Registers
integrated circuit design
formal verification
Measurement
Compositionality
uncertainty
Vulnerability Analysis
electronic engineering computing
data flow

biblio

Implementation and Comparison of SPA and DPA Countermeasures for Elliptic Curve Point Multiplication

Submitted by grigby1 on Fri, 06/26/2020 - 11:55am

Logic gates
Simple Power Analysis Attack
side channel analysis attacks
Scalability
Resiliency
resilience
public key cryptography
pubcrawl
power analysis attacks
Metrics
Differential Power Analysis Attack
integrated circuits
hardware description languages
elliptic curve point multiplication
elliptic curve cryptosystems
Elliptic Curve Cryptosystem
Elliptic curve cryptography
DPA countermeasures
differential power analysis attacks

biblio

A Hierarchical Approach to Self-Timed Circuit Verification

Submitted by aekwall on Mon, 03/16/2020 - 9:39am

asynchronous circuit modeling
timing circuits
self-timed circuit verification
non deterministic behavior
mechanical theorem proving
link-joint style
link joint model
Latches
iterative self-timed circuits
hierarchical verification
hardware description language
greatest common divisor circuit model
greatest common divisor
flip-flops
combinational circuits
asynchronous circuit verification
Resiliency
arbitrated merge
ACL2 theorem prover
Theorem Proving
scalable verification
hardware description languages
Integrated circuit modeling
Wires
Compositionality
Predictive Metrics
Scalability
timing
Logic gates
Iterative methods
Computational modeling
pubcrawl

biblio

Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes

Submitted by aekwall on Mon, 03/16/2020 - 9:39am

SystemC VP
Computer simulation
design verification
Electronic System Level
semiconductor industry
simulation behavior
Simulation-based Verification
SystemC
SystemC language
scalable verification
SystemC-based virtual prototypes
systems analysis
TLM
TLM-2.0 rules
Transaction Level Modeling framework
Virtual Prototype
virtual prototyping
Scalability
Protocols
Resiliency
pubcrawl
Computational modeling
standards
Formal Specification
verification
timing
Hardware
Predictive Metrics
Prototypes
Compositionality
formal verification
Clang
hardware description languages
Object oriented modeling

biblio

Self-Healing Approach for Hardware Neural Network Architecture

Submitted by grigby1 on Mon, 02/17/2020 - 4:12pm

hardware nodes
VHDL
Training
spare node
self-healing networks
self-healing approach results
self-healing
Resiliency
resilience
Redundancy
pubcrawl
Neurons
neural net architecture
neural chips
neighbor node
modest area overhead
Altira 10 GX FPGA
hardware neural Network architecture
hardware description languages
Hardware
field programmable gate arrays
faulty node
Fault-tolerant
fault tolerant computing
fault detection
Evolvable hardware
Embryonic hardware
current self-healing neural network
composability
complex neural network
Biological neural networks
artificial neural network

biblio

Optimizing Quantum Circuits for Modular Exponentiation

Submitted by aekwall on Mon, 01/20/2020 - 10:48am

pubcrawl
verilog implementation
tools
scalable synthesis methods
Scalability
reversible modular exponentiation function
Resiliency
Qubit
Quantum error correction
Quantum Error Correcting Codes (QECC)
quantum computing
quantum computers
quantum circuits
quantum architectures
Quantum Algorithm(QA)
computer architecture
modular exponentiation functions
modular exponentiation
Logic gates
logic designs
logic design
logic circuits
linear nearest neighbor property
Linear Nearest Neighbor (LNN)
Hardware design languages
hardware description languages
exponentiation functions
exponentiation
error correction

biblio

Architecture Analysis and Verification of I3C Protocol

Submitted by grigby1 on Tue, 11/12/2019 - 3:29pm

SoC
MIPI
Monitoring
Pins
policy-based governance
privacy
protocol verification
Protocols
pubcrawl
IP networks
system Verilog
test environments
Universal Verification Methodology
UVM
verification components
verification environment
VLSI
formal verification
back end design
base class library
Clocks
collaboration
composability
Compositionality
Conferences
digital integrated circuits
Aerospace electronics
front end design
hardware description languages
I3C
I3C bus protocol
improved inter integrated circuit
integrated circuit design
integrated circuit testing

biblio

Design of Generic Verification Procedure for IIC Protocol in UVM

Submitted by grigby1 on Tue, 11/12/2019 - 3:29pm

SDA(Serial data line)
Monitoring
policy-based governance
privacy
product development
program verification
protocol verification
Protocols
pubcrawl
SCL(Serial clock line)
Mentor graphic Questasim 10.4e
standard method
Synchronization
Universal Verification Methodology
UVC(Universal verification component)
UVM
UVM(Univeral verification methodology)
Verilog
Vivado
field buses
APB(Advanced peripheral bus)
bugs
Clocks
code coverage
collaboration
composability
Compositionality
Conferences
DUT(Design under test)
Aerospace electronics
functional coverage
generic verification procedure
hardware description languages
Hardware design languages
IIC bus protocol
IIC controller
IIC protocol
Libraries

biblio

Robust Functional Verification Framework Based in UVM Applied to an AES Encryption Module

Submitted by grigby1 on Fri, 06/28/2019 - 9:36am

Measurement
Verification Framework
UVM
Universal Verification Methodology
System Verilog-based functional verification
standards
scalable verification
Scalability
robust functional verification framework
Resiliency
resilience
Reliability engineering
pubcrawl
Metrics
AES encryption module
information-security applications
Industries
high-level designs
hardware description languages
functional verification
formal verification
encryption
direct verification methodologies
digital design industry
design requirements
Cryptography
Compositionality

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Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

hardware description languages

A Support Vector Machine Algorithm for PIR Special Processor

QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment

Implementation and Comparison of SPA and DPA Countermeasures for Elliptic Curve Point Multiplication

A Hierarchical Approach to Self-Timed Circuit Verification

Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes

Self-Healing Approach for Hardware Neural Network Architecture

Optimizing Quantum Circuits for Modular Exponentiation

Architecture Analysis and Verification of I3C Protocol

Design of Generic Verification Procedure for IIC Protocol in UVM

Robust Functional Verification Framework Based in UVM Applied to an AES Encryption Module