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National Science Foundation

Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

CPS-VO

hardware engine

biblio

Visible to the public System architectural design of a hardware engine for moving target IPv6 defense over IEEE 802.3 Ethernet

Submitted by K_Hooper on Wed, 02/28/2018 - 11:38am
  • obscuration technique
  • Logic gates
  • Metrics
  • moving target defense
  • moving target IPv6 defense
  • MT6D processor
  • network address
  • network infrastructure
  • network level
  • network packet processor
  • network processor
  • network time protocol listener
  • keyed access
  • operating system kernel
  • operating system kernels
  • personal area networks
  • Protocols
  • pubcrawl
  • Register Transfer Level network security processor implementation
  • Resiliency
  • Routing protocols
  • RTL development
  • system architectural design
  • system level functions
  • federal networks
  • application specific integrated circuits
  • ASIC
  • CISC architecture
  • Clocks
  • collaboration
  • complex instruction set computer architecture
  • composability
  • computer network security
  • cryptographic dynamic addressing
  • Encapsulation
  • Engines
  • application specific integrated circuit variant
  • FPGA
  • Hardware
  • hardware engine
  • HE-MT6D
  • Homeland Security Cyber Security Division
  • IEEE 802.3 Ethernet
  • Instruction sets
  • internet
  • IP networks
  • IPv6
  • ipv6 security

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