Skip to Main Content Area
CPS-VO
Contact Support
Browse
Calendar
Announcements
Repositories
Groups
Search
Search for Content
Search for a Group
Search for People
Search for a Project
Tagcloud
› Go to login screen
Not a member?
Click here to register!
Forgot username or password?
Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
ASIC
biblio
A Faster Hardware Implementation of the AES S-box
Submitted by grigby1 on Wed, 07/13/2022 - 1:12pm
pubcrawl
Resiliency
delays
Libraries
resilience
Inverters
ASIC
Scalability
Semiconductor device modeling
Minimization
mathematical models
VHDL
exponentiation
AES S-box
Composite field arithmetic
Logic-minimization heuristics
biblio
Application Specific Integrated Gate-Drive Circuit for Driving Self-Oscillating Gallium Nitride Logic-Level Power Transistors
Submitted by grigby1 on Fri, 04/24/2020 - 4:08pm
Power transistors
gate-driver functional behaviour
high-speed floating level-shifter
high-voltage transistors
III-V semiconductors
integrated complementary metal-oxide-semiconductor gate-drivers
logic-level power transistors
low-power electronics
MOSFET
package bondwire connections
parallel LC resonant tank
parasitic capacitance
PCB
power density
gate-driver
printed circuit design
prototype printed circuit board design
reset circuitry
Self-oscillating
self-oscillating gallium nitride
self-oscillating gate-drive
switch-mode power supplies
switched mode power supplies
Switching circuits
wide band gap semiconductors
wide bandgap power semiconductors
oscillating behaviors
ASIC
pubcrawl
resilience
Resiliency
privacy
composability
integrated circuit design
Metrics
Resistance
CMOS integrated circuits
Analog integrated circuit
application specific integrated circuits
application specific integrated gate-drive circuit
Logic gates
capacitance 56.7 pF
class-E resonant inverter
CMOS gate-drivers
driver circuits
electrostatic discharge
electrostatic discharge diode
Electrostatic discharges
ESD diode
fabricated gate-driver
gallium compounds
gan
gate drive technologies
biblio
Hardware implementation of Piccolo Encryption Algorithm for constrained RFID application
Submitted by aekwall on Mon, 02/10/2020 - 11:44am
piccolo encryption algorithm
4 input LUTs
64 bits block size
area optimization
ASIC
constrained RFID application
different design strategies
efficient hardware architecture
Fiestel structure
hardware design
hardware metrics
low resource applications
optimized area
Piccolo Algorithm
128 bits
piccolo lightweight algorithm
radiofrequency identification
relevant lightweight block ciphers
severe security concerns
supports high speed
Throughput.
tremendous pace
ultra-lightweight applications
variable key size
word length 64.0 bit
word length 80.0 bit
Xillinx
Microelectronics Security
security applications
field programmable gate arrays
FPGA
Cryptography
encryption
Internet of Things
telecommunication security
Hardware
Table lookup
IoT applications
smart devices
Resiliency
pubcrawl
composability
IoT
RFID
Throughput
Ciphers
security issues
Predictive Metrics
private information
word length 128.0 bit
Hardware Implementation
hardware resources
lightweight cryptographic algorithms
S-box
lightweight cryptography
biblio
System architectural design of a hardware engine for moving target IPv6 defense over IEEE 802.3 Ethernet
Submitted by K_Hooper on Wed, 02/28/2018 - 11:38am
obscuration technique
Logic gates
Metrics
moving target defense
moving target IPv6 defense
MT6D processor
network address
network infrastructure
network level
network packet processor
network processor
network time protocol listener
keyed access
operating system kernel
operating system kernels
personal area networks
Protocols
pubcrawl
Register Transfer Level network security processor implementation
Resiliency
Routing protocols
RTL development
system architectural design
system level functions
federal networks
application specific integrated circuits
ASIC
CISC architecture
Clocks
collaboration
complex instruction set computer architecture
composability
computer network security
cryptographic dynamic addressing
Encapsulation
Engines
application specific integrated circuit variant
FPGA
Hardware
hardware engine
HE-MT6D
Homeland Security Cyber Security Division
IEEE 802.3 Ethernet
Instruction sets
internet
IP networks
IPv6
ipv6 security
biblio
Implementation and optimization of A5-1 algorithm on coarse-grained reconfigurable cryptographic logic array
Submitted by grigby1 on Wed, 02/21/2018 - 1:41pm
resource allocation
Microelectronic Security
Noise measurement
performance optimization
pubcrawl
real-time requirements
reconfigurable architectures
resilience
Resiliency
Metrics
resource consumption
resource-based path seeking algorithm
RPS adaptive algorithm
shift registers
stream cipher
telecommunication security
Throughput
voice data encryption
coarse-grained reconfigurable cryptographic logic array
A5-1 algorithm optimization
Algorithm design and analysis
application specific integrated circuits
ASIC
bit rate 162.87 Mbit/s
cellular radio
CGRCA
Ciphers
A5-1
composability
Conferences
Cryptography
field programmable gate arrays
FPGA
frequency 162.87 MHz
GSM
biblio
Hermes: Secure heterogeneous multicore architecture design
Submitted by grigby1 on Wed, 02/21/2018 - 1:37pm
Program processors
trust-aware routing algorithm
tenant security
system-on-chip
system-level integration
SoC design
security
secure heterogeneous multicore architecture design
secure cores
Scalability
Resiliency
resilience
pubcrawl
programmable secure router interface
programmable RISC cores
programmable distributed group key management scheme
accelerator function units
nonsecure cores
multiprocessing systems
multiple processing elements
multilevel user-defined security
Multicore processing
multicore computing security
Multicore Computing
Metrics
Hermes architecture
Hardware
general-purpose system-on-chip architectures
DSP
ASIC
application executable code
biblio
Platform agnostic, scalable, and unobtrusive FPGA network processor design of moving target defense over IPv6 (MT6D) over IEEE 802.3 Ethernet
Submitted by grigby1 on Tue, 01/16/2018 - 6:31pm
IPv6
RTL-based Network Time Protocol v4 synchronization
Resiliency
register transfer level logic
pubcrawl
network-based keyed access
network processor
MT6D
moving target defense over IPv6
moving target defense
modular crypto engine
Metrics
low power wireless personal area networks
Local area networks
IPv6 interfaces
application specific integrated circuits
IP networks
Instruction sets
IEEE 802.3 Standard
IEEE 802.3 Ethernet
FPGA
field programmable gate arrays
EPON
embedded application-specified integrated circuit
Electrical Engineering
Cryptography
Computers
complex instruction set computer instruction set architecture
ASIC
