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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
network processor
biblio
System architectural design of a hardware engine for moving target IPv6 defense over IEEE 802.3 Ethernet
Submitted by K_Hooper on Wed, 02/28/2018 - 10:38am
obscuration technique
Logic gates
Metrics
moving target defense
moving target IPv6 defense
MT6D processor
network address
network infrastructure
network level
network packet processor
network processor
network time protocol listener
keyed access
operating system kernel
operating system kernels
personal area networks
Protocols
pubcrawl
Register Transfer Level network security processor implementation
Resiliency
Routing protocols
RTL development
system architectural design
system level functions
federal networks
application specific integrated circuits
ASIC
CISC architecture
Clocks
collaboration
complex instruction set computer architecture
composability
computer network security
cryptographic dynamic addressing
Encapsulation
Engines
application specific integrated circuit variant
FPGA
Hardware
hardware engine
HE-MT6D
Homeland Security Cyber Security Division
IEEE 802.3 Ethernet
Instruction sets
internet
IP networks
IPv6
ipv6 security
biblio
Platform agnostic, scalable, and unobtrusive FPGA network processor design of moving target defense over IPv6 (MT6D) over IEEE 802.3 Ethernet
Submitted by grigby1 on Tue, 01/16/2018 - 5:31pm
IPv6
RTL-based Network Time Protocol v4 synchronization
Resiliency
register transfer level logic
pubcrawl
network-based keyed access
network processor
MT6D
moving target defense over IPv6
moving target defense
modular crypto engine
Metrics
low power wireless personal area networks
Local area networks
IPv6 interfaces
application specific integrated circuits
IP networks
Instruction sets
IEEE 802.3 Standard
IEEE 802.3 Ethernet
FPGA
field programmable gate arrays
EPON
embedded application-specified integrated circuit
Electrical Engineering
Cryptography
Computers
complex instruction set computer instruction set architecture
ASIC
biblio
Attacks and Defenses in the Data Plane of Networks
Submitted by Heather Lucas on Wed, 09/17/2014 - 5:33pm
NetFPGA
software-programmable network processors
software vulnerabilities
security issues
Routing protocols
programmable router
Program processors
processing monitor
packet processing software
packet forwarding
network security
network routers
network processor
network attack
Computer crime
logic devices
internet
hardware-based defense mechanism
field programmable gate arrays
embedded systems
embedded system security
denial-of-service attack
data plane
custom-logic hardware
control plane
computer networks
computer network security
biblio
Secure-by-construction Composable Componentry for Network Processing
Submitted by Heather Lucas on Wed, 09/17/2014 - 5:32pm
Embedded Software
Systems Engineering
Science of Security
CPS Technologies
Foundations
foundations
Tamper-Proof/Resistant Designs
systems engineering
Symmetric Cryptography and Hash Functions
stream processing
Security in Hardware
secure-by-construction
Science of Security
network processor
line-speed processor
hardware-software co-design
100 Gbps
Embedded Systems Security
embedded software
embedded hardware
Database and Storage Security
Data Anonymization and Sanitization
Cryptography
CPS Technologies
Block and Stream Ciphers
ACM CCS
ACM CCS
Cryptography
Block and Stream Ciphers
Data Anonymization and Sanitization
Embedded Systems Security
Database and Storage Security
Tamper-Proof/Resistant Designs
Security in Hardware
Symmetric Cryptography and Hash Functions
file
Secure-by-Construction Composable Componentry for Network Processing (poster)
Submitted by Heather Lucas on Wed, 06/04/2014 - 8:43am. Contributors:
Lisa Durbeck
Peter Athanas
Nicholas Macias
100 Gbps
hardware-software co-design
network processor
secure-by-construction
stream processing
HotSoS 2014
Academia
Poster
Posters
Posters
Embedded Systems Security
Security in Hardware
