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National Science Foundation

Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

CPS-VO

secure scan architecture

biblio

Visible to the public A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks

Submitted by grigby1 on Fri, 04/05/2019 - 10:29am
  • memory attack
  • Side-channel attack
  • side channel attack
  • security level
  • security
  • secure scan architecture
  • scan design key generator
  • Scalability
  • Resiliency
  • resilience
  • Random access memory
  • pubcrawl
  • memory cold boot attack
  • memory attacks
  • Chained Attacks
  • integrated circuit testing
  • Hardware Security
  • Generators
  • flip-flops
  • dynamic-key secure scan structure
  • dynamic-key secure DFT structure
  • dynamic key generation
  • Discrete Fourier transforms
  • design for testability
  • design for test technology
  • Cryptography
  • Controllability
  • Clocks
biblio

Visible to the public Secure Scan Architecture Using Clock and Data Recovery Technique

Submitted by grigby1 on Thu, 02/14/2019 - 11:22am
  • fault coverage
  • Voltage control
  • System recovery
  • security threats
  • security of data
  • secure scan architecture
  • Scan Architecture
  • Resiliency
  • resilience
  • pubcrawl
  • Observability
  • Hardware Security
  • fault diagnosis
  • authentication
  • encoding
  • DLL
  • DfT technique
  • DfT
  • design for testability
  • delays
  • Controllability
  • computer architecture
  • Clocks
  • clock-data recovery technique
  • CDR

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