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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
flip-flops
biblio
Work-in-Progress: Towards a Smaller than Grain Stream Cipher: Optimized FPGA Implementations of Fruit-80
Submitted by aekwall on Fri, 03/03/2023 - 10:57am
lightweight cryptography
Lightweight Ciphers
stream cipher
parallelism
Grain
Fruit-80
FPGA implementation
flip-flops
Computer aided software engineering
field programmable gate arrays
cyber-physical systems
Ciphers
Resiliency
Scalability
pubcrawl
optimization
Internet of Things
embedded systems
biblio
Highly Area-Efficient Implementation of Modular Multiplication for Elliptic Curve Cryptography
Submitted by aekwall on Mon, 02/15/2021 - 4:55pm
koblitz Curve
Virtex-7 FPGA technology
Throughput
Table lookup
Scalability
Resiliency
Registers
public-key cryptosystem
Public Key Cryptography (PKC)
public key cryptography
pubcrawl
multiplying circuits
Metrics
LUT-FF pairs
logic design
256-bit modified interleaved modular multiplication
Interleaved Modular Multiplication (IMM)
IMM
hardware implementation design
Hardware Architecture (HA)
Hardware
flip-flops
field programmable gate arrays
Field Programmable Gate Array (FPGA)
Elliptic curve cryptography (ECC)
Elliptic curve cryptography
ECC operation
Cryptography
cryptographic operation
computer architecture
biblio
A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis
Submitted by aekwall on Mon, 11/09/2020 - 1:41pm
reverse engineering
testable key-controlled FSM synthesis scheme
state-transition
reverse engineering attacks
nongroup additive cellular automata
finite-state-machine synthesis
digital system
D1*CAdual
D1*CA
cellular automata guided obfuscation strategy
ip protection
IP piracy
cellular automata
security
flip-flops
Additives
finite state machines
Silicon
automata
industrial property
Logic gates
policy-based governance
composability
pubcrawl
Resiliency
biblio
Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design
Submitted by aekwall on Mon, 11/09/2020 - 1:41pm
low-overhead robust RTL signature
FIR filters
IP piracy
flip-flops
covert signature embedding process
digital signal processor
DSP core protection
DSP-MP IP core
IP vendors
FIR filter
Multimedia Processor
nonsignature FIR RTL design
register-transfer level
reusable Intellectual Property cores
robust IP owner
secured smart CE device
smart CE design
smart Consumer Electronics devices
Registers
Hardware
Resiliency
pubcrawl
composability
policy-based governance
digital signatures
microprocessor chips
Multiplexing
IP networks
digital signal processing chips
Finite impulse response filters
adders
logic circuits
logic design
Latches
Consumer electronics
biblio
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic
Submitted by aekwall on Mon, 11/09/2020 - 1:40pm
block logic
Trojan insertion
IP core locking block logic
Intellectual Property cores
Integrated Circuit design flow
ILB
hardware threats
functionally obfuscated design
functional obfuscation based security mechanism
functional obfuscation
flip-flops
flip-flop
DSP design
digital signal processing core
consumer electronics systems
combinational logic
Cryptography
IP core
IC design flow
IP piracy
Consumer electronics
combinational circuits
DSP
logic design
DSP core
digital signal processing chips
industrial property
policy-based governance
composability
pubcrawl
Resiliency
biblio
A Hierarchical Approach to Self-Timed Circuit Verification
Submitted by aekwall on Mon, 03/16/2020 - 10:39am
asynchronous circuit modeling
timing circuits
self-timed circuit verification
non deterministic behavior
mechanical theorem proving
link-joint style
link joint model
Latches
iterative self-timed circuits
hierarchical verification
hardware description language
greatest common divisor circuit model
greatest common divisor
flip-flops
combinational circuits
asynchronous circuit verification
Resiliency
arbitrated merge
ACL2 theorem prover
Theorem Proving
scalable verification
hardware description languages
Integrated circuit modeling
Wires
Compositionality
Predictive Metrics
Scalability
timing
Logic gates
Iterative methods
Computational modeling
pubcrawl
biblio
Hardware Trojans Detection at Register Transfer Level Based on Machine Learning
Submitted by grigby1 on Wed, 02/26/2020 - 4:37pm
Libraries
Trojan horses
trojan horse detection
training database
Training
supply chain security
source code (software)
shift registers
server-client mechanism
RTL source codes
Resiliency
resilience
register transfer level
pubcrawl
machine-learning-based detection method
circuit features extraction
learning (artificial intelligence)
invasive software
integrated circuits design process
Integrated circuit modeling
integrated circuit design
Hardware Trojans library
Hardware Trojans detection
Hardware
flip-flops
feature extraction
electronic engineering computing
database management systems
cyber physical systems
biblio
A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks
Submitted by grigby1 on Fri, 04/05/2019 - 10:29am
memory attack
Side-channel attack
side channel attack
security level
security
secure scan architecture
scan design key generator
Scalability
Resiliency
resilience
Random access memory
pubcrawl
memory cold boot attack
memory attacks
Chained Attacks
integrated circuit testing
Hardware Security
Generators
flip-flops
dynamic-key secure scan structure
dynamic-key secure DFT structure
dynamic key generation
Discrete Fourier transforms
design for testability
design for test technology
Cryptography
Controllability
Clocks
file
POSTER: Non-Volatile Computing for Embedded Cyber-Physical Systems
Submitted by edwardsuh on Mon, 09/14/2015 - 4:46pm. Contributors:
G. Edward Suh
Wing-kei S. Yu
Shantanu Rajwade
Edwin Kan
Embedded Software
Systems Engineering
Resilient Systems
CPS Technologies
Foundations
Cornell University
flash transistors
flip-flops
SDRAM
SRAM
0932069
National CPS PI Meeting 2010
Posters
Academia
Poster
biblio
A Cross-Layer Secure Communication Model Based on Discrete Fractional Fourier Fransform (DFRFT)
Submitted by BrandonB on Tue, 05/05/2015 - 10:21am
eavesdropper
telecommunication security
signal processing applications
signal processing
security codes
security code
security
secure communication systems
physical layer security
OFDM
Mobile communication
flip-flops
error-free legitimate channel
codes
distortion
distort signal parameter
discrete fractional Fourier fransform
Discrete Fourier transforms
DFRFT
crosslayer
cross-layer strong mobile communication secure model
cross-layer secure communication model
cross-layer DFRFT security communication model
cross-layer
Constellation diagram
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