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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
design for testability
biblio
Protection Profile Bricks for Secure IoT Devices
Submitted by grigby1 on Thu, 08/04/2022 - 4:04pm
Internet of Things
security
Monitoring
pubcrawl
resilience
Resiliency
privacy
Object recognition
Communication system security
composability
Microprogramming
lighting
design for testability
trusted platform modules
biblio
Secured Test Pattern Generators for BIST
Submitted by grigby1 on Fri, 07/29/2022 - 8:44am
intellectual property
pattern locks
TPG
overproduction
BIST
logic locking
design for testability
built-in self-test
Hardware Security
reverse engineering
pubcrawl
side-channel attacks
integrated circuits
privacy
Scalability
Hardware
Resiliency
resilience
Human behavior
biblio
LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment
Submitted by grigby1 on Fri, 07/29/2022 - 8:44am
supply chains
pattern locks
untrusted foundry
Manufacturing test
logic locking
design for testability
Costs
Semiconductor device modeling
reverse engineering
Logic gates
manufacturing
Scalability
system-on-chip
Resiliency
resilience
Human behavior
pubcrawl
biblio
An effective technique preventing differential cryptanalysis attack
Submitted by grigby1 on Wed, 03/17/2021 - 11:42am
Adaptive scan chain
Chained Attacks
traditional scan chain
plaintexts differs
plaintext analysis technique
plaintext analysis module
plaintext analysis circuit
differential cryptanalysis attack
different scan chain
design for testability
controller circuit
complicated scan chain
adaptive scan chain structure
adaptive scan chain circuit
Logic gates
Hardware Security
Watermarking
Switches
Registers
Scalability
integrated circuit testing
Mathematical model
AES
Hardware
Resiliency
resilience
pubcrawl
Cryptography
biblio
A Dynamic-Key Secure Scan Structure Against Scan-Based Side Channel and Memory Cold Boot Attacks
Submitted by grigby1 on Fri, 04/05/2019 - 9:29am
memory attack
Side-channel attack
side channel attack
security level
security
secure scan architecture
scan design key generator
Scalability
Resiliency
resilience
Random access memory
pubcrawl
memory cold boot attack
memory attacks
Chained Attacks
integrated circuit testing
Hardware Security
Generators
flip-flops
dynamic-key secure scan structure
dynamic-key secure DFT structure
dynamic key generation
Discrete Fourier transforms
design for testability
design for test technology
Cryptography
Controllability
Clocks
biblio
Secure Scan Architecture Using Clock and Data Recovery Technique
Submitted by grigby1 on Thu, 02/14/2019 - 10:22am
fault coverage
Voltage control
System recovery
security threats
security of data
secure scan architecture
Scan Architecture
Resiliency
resilience
pubcrawl
Observability
Hardware Security
fault diagnosis
authentication
encoding
DLL
DfT technique
DfT
design for testability
delays
Controllability
computer architecture
Clocks
clock-data recovery technique
CDR
biblio
Security vulnerability analysis of design-for-test exploits for asset protection in SoCs
Submitted by grigby1 on Tue, 12/12/2017 - 12:31pm
integrity
test structures
system-on-chips
system-on-chip
SoC integration
Security Policies Analysis
secure microprocessors
secret keys
pubcrawl
policy-based governance
memory read-write functions
Logic gates
IP networks
internal modules
asset protection
information leakage vulnerabilities
encryption algorithms
encryption
Discrete Fourier transforms
design-for-test exploits
design for testability
Cryptography
Controllability
control finite state machines
confidentiality
collaboration
availability policies
automated security vulnerability analysis framework
biblio
Slack removal for enhanced reliability and trust
Submitted by BrandonB on Wed, 05/06/2015 - 10:34am
Small Delay Defects
mission-critical application
pattern count
reliability enhancement
security of data
security vulnerabilities
security-critical application
slack removal
Slacks
malicious circuitries
test quality
testing
timing slacks
transition fault patterns
Trojan horses
trust enhancement
Wires
fabrication
care bit density intact
Circuit faults
delay defect detection
delay defects
delay unit insertion
delays
design for testability
design technique
At-speed Testing
Hardware
hardware trojan
Hardware Trojans
integrated circuit reliability
logic circuits
Logic gates
logic testing
