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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
benchmark test set
biblio
A New Hardware Logic Circuit for Evaluating Multi-Processor Chip Security
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
manufacturing processes
research hotspots
replay-type hardware Trojan
on-chip systems
NoC vulnerability
NoC power consumption
NoC hardware security
NoC
new hardware logic circuit
network-on-chip
network throughput reduction
multiprocessor chip security
multiprocessing systems
pubcrawl
logic circuits
invasive software
inter-core interconnection method
Integrated circuit interconnections
defense strategies
communication performance optimization
benchmark test set
Metrics
resilience
Resiliency
Scalability
network on chip security
