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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
logic circuits
biblio
Security Metrics for Logic Circuits
Submitted by grigby1 on Fri, 01/13/2023 - 4:19pm
pubcrawl
Metrics
Hardware
Entropy
logic locking
parallel processing
Power demand
Current measurement
Sensitivity
Security Metrics
Hardware Security
obfuscation
logic circuits
biblio
Assessing Trustworthiness of IoT Applications Using Logic Circuits
Submitted by grigby1 on Wed, 08/03/2022 - 4:13pm
logic circuits
Internet of Things
Training
machine learning
machine learning algorithms
pubcrawl
Software
Computational modeling
composability
Software algorithms
trustworthiness
trust
computationally constrained devices
biblio
Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics
Submitted by aekwall on Thu, 05/19/2022 - 1:41pm
Human Factors
Integrated optics
logic circuits
Logic gates
Metrics
nanophotonics
Optical computing
Optical design
Optical detectors
pubcrawl
Resistance
Scalability
security
Side-channel attack
Tamper resistance
Tamper-Resistance
biblio
Implementation of Quantum Gates based Logic Circuits using IBM Qiskit
Submitted by grigby1 on Tue, 08/31/2021 - 1:11pm
quantum computing
security
pubcrawl
Computers
encoding
IBM Quantum
instantiation
logic circuits
Logic gates
Qiskit
quantum gate
Qubit
Registers
Scalability
biblio
Physical Unclonable Functions (PUFs) Entangled Trusted Computing Base
Submitted by aekwall on Mon, 12/07/2020 - 12:23pm
Predictive Metrics
trusted platform modules
trusted computing base
Trusted Computing
SW-PUF measurements
software measurement physical unclonable function
Software measurement
software instruction
Software
Semiconductor device measurement
Scalability
Resiliency
Reliability
pubcrawl
program execution
processor chip ALU silicon biometrics
Clocks
Pollution measurement
physical unclonable functions
particular program instruction
neural style transfer
microprocessor chips
logic design
logic circuits
field programmable gate arrays
digital signatures
delays
data-dependent delay
cyber-physical system security
copy protection
composability
biblio
Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design
Submitted by aekwall on Mon, 11/09/2020 - 1:41pm
low-overhead robust RTL signature
FIR filters
IP piracy
flip-flops
covert signature embedding process
digital signal processor
DSP core protection
DSP-MP IP core
IP vendors
FIR filter
Multimedia Processor
nonsignature FIR RTL design
register-transfer level
reusable Intellectual Property cores
robust IP owner
secured smart CE device
smart CE design
smart Consumer Electronics devices
Registers
Hardware
Resiliency
pubcrawl
composability
policy-based governance
digital signatures
microprocessor chips
Multiplexing
IP networks
digital signal processing chips
Finite impulse response filters
adders
logic circuits
logic design
Latches
Consumer electronics
biblio
DLockout: A Design Lockout Technique for Key Obfuscated RTL IP Designs
Submitted by aekwall on Mon, 11/09/2020 - 1:40pm
nondestructive manner
Datapath
datapath intensive IPs
Design Lockout
DLockout
key obfuscated RTL IP designs
key obfuscated RTL module
key obfuscation
key-based obfuscation techniques
legacy IP
common side-channel attacks
obfuscation logic output
overproduction
robust design lockout technique
RTL Obfuscation
semiconductor supply chain
storage capacity 128 bit
storage capacity 32 bit
storage capacity 64 bit
typical design corner
Computer crime
Cryptography
Hardware
security
Software
Resiliency
pubcrawl
composability
policy-based governance
logic locking
IP networks
process control
reverse engineering
Integrated circuit modeling
Registers
logic circuits
controller
IP piracy
applied key
biblio
A Novel PUF based Logic Encryption Technique to Prevent SAT Attacks and Trojan Insertion
Submitted by aekwall on Mon, 11/09/2020 - 1:33pm
intellectual property/IC
IP piracy
SAT attack
hardware obfuscation
Anti-Trojan insertion algorithm
Controllability
copy protection
design-for-trust
hardware Trojan insertion
HT insertion
hardware trojan
logic encryption methods
logic encryption techniques
logic locking
PUF based logic encryption technique
PUF-based encryption
Rare Signal
reverse engineering attack
unique encryption
Hardware Security
encryption
Hardware
invasive software
Resiliency
pubcrawl
composability
policy-based governance
Trojan horses
integrated circuits
Cryptography
Topology
Logic gates
industrial property
reverse engineering
integrated circuit design
logic circuits
Physical Unclonable Function
encryption key
biblio
Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method
Submitted by aekwall on Mon, 11/09/2020 - 1:32pm
integrated circuit industry
IP piracy
application specific integrated circuits
ASIC technology
circuit complexity
combinational circuits
finite state machine
FSM obfuscation method
hardware obfuscation method
Hardware Security
IP overproduction
ITC99 circuit benchmarks
logic encryption
Logic masking
Mystic obfuscation approach
Mystic protection method
mystifying IP cores
Logic gates
Hardware
Resiliency
pubcrawl
composability
policy-based governance
Production
Complexity theory
microprocessor chips
IP networks
obfuscation
reverse engineering
encoding
finite state machines
logic circuits
logic design
size 45.0 nm
biblio
IC/IP Piracy Assessment of Reversible Logic
Submitted by aekwall on Mon, 11/09/2020 - 1:31pm
proper-size reversible functions
BDD
binary decision diagrams
embedded function
garbage outputs
IC-IP piracy assessment
IC/IP piracy
intellectual property piracy
Number of embeddings
ancillary inputs
QMDD
quantum multivalued decision diagrams
regular functions
Reversible logic
reversible logic circuits
reversible logic synthesis tools
IP piracy
IP networks
adiabatic computing
logic design
logic circuits
adders
Integrated circuit modeling
industrial property
Logic gates
quantum computing
Trojan horses
policy-based governance
composability
pubcrawl
Resiliency
embedded systems
security
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