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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
multiprocessing systems
biblio
Lightweight Monitoring Scheme for Flooding DoS Attack Detection in Multi-Tenant MPSoCs
Submitted by grigby1 on Tue, 03/01/2022 - 3:20pm
composability
Floods
Integrated circuit modeling
Metrics
Monitoring
multiprocessing systems
network on chip security
network-on-chip
Payloads
pubcrawl
resilience
Resiliency
Scalability
Task Analysis
biblio
SS3: Security-Aware Vendor-Constrained Task Scheduling for Heterogeneous Multiprocessor System-on-Chips
Submitted by aekwall on Mon, 06/28/2021 - 11:39am
security
Task Analysis
Resiliency
pubcrawl
composability
policy-based governance
Trojan horses
MPSoC
sensors
Minimization
hardware trojan
task scheduling
intellectual property
IP vendor
multiprocessing systems
intellectual property security
biblio
Performance Analysis of IDS Snort and IDS Suricata with Many-Core Processor in Virtual Machines Against Dos/DDoS Attacks
Submitted by grigby1 on Fri, 04/09/2021 - 10:32am
Central Processing Unit
testing
virtual machine
Performance analysis
IDS
Telecommunications
transport protocols
DoS
denial-of-service attack
operating systems (computers)
IDS Snort version
IDS Suricata
many-core processor
physical machine
Snort
Suricata
TCP Flood attack test
IP networks
resilience
DDoS
virtual machines
Virtual machining
DDoS Attacks
multiprocessing systems
telecommunication traffic
composability
Wireless communication
intrusion detection system
wireless sensor networks
microprocessor chips
computer network security
Resiliency
pubcrawl
biblio
A Formal Model for the Automatic Configuration of Access Protection Units in MPSoC-Based Embedded Systems
Submitted by grigby1 on Mon, 03/29/2021 - 10:56am
Resiliency
MPSoC-based embedded systems
multiple processing cores
multiprocessing systems
multiprocessor system-on-chip
on-chip isolation
pubcrawl
real-time systems
resilience
model-based design
Safety
safety-critical embedded system
safety-critical software
security
security-critical embedded system
system-level isolation
system-on-chip
timing
dedicated access protection units
access permissions
access protection
access protection unit
authorisation
Code Generation
composability
configuration code
Data protection
abstract permission declarations
embedded systems
formal model
Hardware
heterogeneous system-on-chip platforms
information flow requirements
information flow tracking
internal communication links
Metrics
biblio
On Countermeasures Against the Thermal Covert Channel Attacks Targeting Many-core Systems
Submitted by grigby1 on Wed, 02/10/2021 - 11:52am
Bit error rate
three-step countermeasure
thermal covert channel attacks
Thermal Covert Channel
TCC attack
signal frequency scanning
manycore systems
Many-core systems
dynamic voltage frequency scaling technique
DVFS technique
Defense against Covert Channel Attack
critical defense issue
Multicore processing
signal detection
security of data
covert channels
error statistics
Temperature sensors
Transmitters
Compositionality
Receivers
multiprocessing systems
thermal noise
Scalability
Resiliency
resilience
pubcrawl
biblio
A Fast MPEG’s CDVS Implementation for GPU Featured in Mobile Devices
Submitted by grigby1 on Tue, 12/01/2020 - 3:37pm
GPU-based approach
Human Factors
CDVS information
Central Processing Unit
Compact Descriptors for Visual Search
comparable precision
computation times
Computer applications
Concurrent computing
CPU-based reference implementation
descriptor extraction process
embedded software
fast MPEG CDVS implementation
GPU data structures
parallel algorithms
Image analysis
indexing algorithm
Internet-scale visual search applications
interoperable cross-platform solution
main local descriptor extraction pipeline phases
many-cores embedded graphical processor units
matching algorithm
memory access
Moving Picture Experts Group
MPEG CDVS standard
visual descriptors
Internet-scale Computing Security
data structures
pubcrawl
Human behavior
Metrics
collaboration
resilience
Resiliency
Scalability
internet
storage management
standards
composability
mobile computing
feature extraction
multiprocessing systems
parallel processing
Kernel
Policy Based Governance
Mobile handsets
graphics processing units
visualization
mobile devices
image matching
image retrieval
object detection
Services
biblio
Safe and Secure Data Fusion — Use of MILS Multicore Architecture to Reduce Cyber Threats
Submitted by aekwall on Mon, 11/16/2020 - 1:58pm
multicore-based real-time operating system
data fusion-based systems
flexible software architectures
functional assurance capabilities
High Robustness
high-robustness separation kernel certification
INTEGRITY-178 tuMP
MILS multicore architecture
multicore
multicore processor
cyber-attack space
multiple independent levels
restricted hardware access
RTOS
Separation Kernel
single-core processors
system providers
system security architecture
Resilient Security Architectures
operating systems (computers)
Resiliency
pubcrawl
Software Architecture
sensor fusion
data flows
aerospace computing
safety-critical software
scheduling
telecommunication security
security risks
multiprocessing systems
MILS
air traffic safety
architecture configurations
civil aircraft systems safety
covert channel prevention
cyber threats reduction
biblio
Towards provably-secure performance locking
Submitted by aekwall on Mon, 11/09/2020 - 12:32pm
Electronics packaging
provably-secure performance locking
performance locking
integrated circuit thwarts attacks
functional locking
FabScalar microprocessor
FabScalar
boolean satisfiability (sat)
intellectual property piracy
IP piracy
Degradation
security of data
Clocks
multiprocessing systems
Integrated circuit modeling
Business
policy-based governance
composability
pubcrawl
Resiliency
power aware computing
security
biblio
Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints
Submitted by grigby1 on Mon, 11/02/2020 - 12:36pm
pubcrawl
two-stage performance-constrained task scheduling algorithm
Trojan horses
task scheduling
Task Analysis
system-on-chip
System performance
system level security constraints
security-driven task scheduling
security of data
security
scheduling
Schedules
schedule length
Resiliency
resilience
composability
Processor scheduling
policy-based governance
performance constraints
Multiprocessor System-on-Chips
multiprocessing systems
MPSoC
malicious inclusions
logic design
IP networks
intellectual property security
industrial property
hardware trojan
Hardware
graph theory
delays
biblio
Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core
Submitted by grigby1 on Mon, 10/05/2020 - 1:00pm
SIC
worst-case execution time
WCET analysis
WCET
timing-predictable pipelined processor core
timing predictability
timing compositionality
timing anomalies
timing
Task Analysis
strictly in-order core
standard in-order pipeline design
Silicon carbide
Compositionality
real-time systems
pubcrawl
pipelining
Pipelines
pipeline processing
multiprocessing systems
multicore timing analysis
Multicore processing
multi-core
monotonicity
microprocessor chips
Hardware
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