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National Science Foundation

Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

CPS-VO

IP core design

biblio

Visible to the public Reusable intellectual property core protection for both buyer and seller

Submitted by grigby1 on Thu, 07/30/2020 - 2:05pm
  • intellectual property
  • seller watermark
  • scheduling phase
  • reusable intellectual property core protection
  • register allocation phase
  • latency overhead
  • IP seller
  • IP core protection
  • IP core design
  • design cost overhead
  • Consumer electronics
  • CE devices
  • buyer fingerprint
  • architectural synthesis process
  • ip protection
  • Watermarking
  • logic circuits
  • resource management
  • Metrics
  • Fingerprint recognition
  • Registers
  • composability
  • embedded systems
  • microprocessor chips
  • Resiliency
  • resilience
  • policy-based governance
  • Human Factors
  • Human behavior
  • pubcrawl
  • IP networks
  • logic design

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