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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
logic design
biblio
SRTLock: A Sensitivity Resilient Two-Tier Logic Encryption Scheme
Submitted by grigby1 on Fri, 07/29/2022 - 9:45am
standards
pattern locks
Sensitivity Attack
logic design
0-Injection
sensitivity analysis
SAT attack
logic encryption
Benchmark testing
Logic gates
Scalability
Hardware Security
Hardware
Resiliency
resilience
Human behavior
pubcrawl
encryption
biblio
Hardware Design of Polynomial Multiplication for Byte-Level Ring-LWE Based Cryptosystem
Submitted by aekwall on Mon, 03/15/2021 - 12:10pm
NIST PQC Standardization Process
BRAMs
byte-level modulus
byte-level ring-LWE based cryptosystem
computational time-consuming block
DSPs
high-level synthesis based hardware design methodology
ideal lattice
LAC
multiplication core
high level synthesis
polynomial multiplication
ring learning with error problem
ring LWE
time 4.3985 ns
time 5.052 ns
time 5.133 ns
Vivado HLS compiler
Xilinx Artix-7 family FPGA
NIST
Scalability
lattice-based cryptography
Cryptography
Hardware
Table lookup
learning (artificial intelligence)
Resiliency
pubcrawl
Metrics
field programmable gate arrays
post quantum cryptography
timing
polynomials
Software algorithms
Compositionality
program compilers
compiler security
logic design
biblio
Breaking a fully Balanced ASIC Coprocessor Implementing Complete Addition Formulas on Weierstrass Elliptic Curves
Submitted by aekwall on Mon, 02/15/2021 - 4:56pm
Elliptic curve cryptography (ECC)
Weierstrass elliptic curves
side channel analysis (SCA) attacks
random order execution
point doubling operations
point addition
open-source designs
Montgomery ladder
horizontal SCA attacks
horizontal DPA attacks
hardware accelerators
fully balanced ASIC coprocessor
complete addition formulas
Scalability
application specific integrated circuits
coprocessors
Clocks
logic design
Registers
Elliptic curves
Elliptic curve cryptography
public key cryptography
Metrics
pubcrawl
Resiliency
biblio
Highly Area-Efficient Implementation of Modular Multiplication for Elliptic Curve Cryptography
Submitted by aekwall on Mon, 02/15/2021 - 4:55pm
koblitz Curve
Virtex-7 FPGA technology
Throughput
Table lookup
Scalability
Resiliency
Registers
public-key cryptosystem
Public Key Cryptography (PKC)
public key cryptography
pubcrawl
multiplying circuits
Metrics
LUT-FF pairs
logic design
256-bit modified interleaved modular multiplication
Interleaved Modular Multiplication (IMM)
IMM
hardware implementation design
Hardware Architecture (HA)
Hardware
flip-flops
field programmable gate arrays
Field Programmable Gate Array (FPGA)
Elliptic curve cryptography (ECC)
Elliptic curve cryptography
ECC operation
Cryptography
cryptographic operation
computer architecture
biblio
Physical Unclonable Functions (PUFs) Entangled Trusted Computing Base
Submitted by aekwall on Mon, 12/07/2020 - 12:23pm
Predictive Metrics
trusted platform modules
trusted computing base
Trusted Computing
SW-PUF measurements
software measurement physical unclonable function
Software measurement
software instruction
Software
Semiconductor device measurement
Scalability
Resiliency
Reliability
pubcrawl
program execution
processor chip ALU silicon biometrics
Clocks
Pollution measurement
physical unclonable functions
particular program instruction
neural style transfer
microprocessor chips
logic design
logic circuits
field programmable gate arrays
digital signatures
delays
data-dependent delay
cyber-physical system security
copy protection
composability
biblio
Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design
Submitted by aekwall on Mon, 11/09/2020 - 1:41pm
low-overhead robust RTL signature
FIR filters
IP piracy
flip-flops
covert signature embedding process
digital signal processor
DSP core protection
DSP-MP IP core
IP vendors
FIR filter
Multimedia Processor
nonsignature FIR RTL design
register-transfer level
reusable Intellectual Property cores
robust IP owner
secured smart CE device
smart CE design
smart Consumer Electronics devices
Registers
Hardware
Resiliency
pubcrawl
composability
policy-based governance
digital signatures
microprocessor chips
Multiplexing
IP networks
digital signal processing chips
Finite impulse response filters
adders
logic circuits
logic design
Latches
Consumer electronics
biblio
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic
Submitted by aekwall on Mon, 11/09/2020 - 1:40pm
block logic
Trojan insertion
IP core locking block logic
Intellectual Property cores
Integrated Circuit design flow
ILB
hardware threats
functionally obfuscated design
functional obfuscation based security mechanism
functional obfuscation
flip-flops
flip-flop
DSP design
digital signal processing core
consumer electronics systems
combinational logic
Cryptography
IP core
IC design flow
IP piracy
Consumer electronics
combinational circuits
DSP
logic design
DSP core
digital signal processing chips
industrial property
policy-based governance
composability
pubcrawl
Resiliency
biblio
Hardware Steganography for IP Core Protection of Fault Secured DSP Cores
Submitted by aekwall on Mon, 11/09/2020 - 1:40pm
DSP based IP cores
vendor defined signature
transient fault secured IP cores
signature size
signature free approach
multimedia cores
IP core protection
IP core
high level synthesis
hardware steganography
fault secured DSP cores
Fault secure
entropy value
entropy thresholding
encoding rule
Resiliency
colored interval graph
IP piracy
Steganography
DSP
logic design
digital signal processing chips
Watermarking
industrial property
digital signatures
Entropy
graph theory
policy-based governance
composability
pubcrawl
biblio
Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method
Submitted by aekwall on Mon, 11/09/2020 - 1:32pm
integrated circuit industry
IP piracy
application specific integrated circuits
ASIC technology
circuit complexity
combinational circuits
finite state machine
FSM obfuscation method
hardware obfuscation method
Hardware Security
IP overproduction
ITC99 circuit benchmarks
logic encryption
Logic masking
Mystic obfuscation approach
Mystic protection method
mystifying IP cores
Logic gates
Hardware
Resiliency
pubcrawl
composability
policy-based governance
Production
Complexity theory
microprocessor chips
IP networks
obfuscation
reverse engineering
encoding
finite state machines
logic circuits
logic design
size 45.0 nm
biblio
Customized Locking of IP Blocks on a Multi-Million-Gate SoC
Submitted by aekwall on Mon, 11/09/2020 - 1:31pm
integrated circuit design
VLSI testing
Solid modeling
off-site untrusted fabrication facilities
multiple IP blocks
multimillion-gate SoC
IP block
integrated circuit manufacture
industrial designs
IP piracy
logic design
Erbium
IP networks
industrial property
Logic gates
integrated circuits
logic locking
policy-based governance
composability
pubcrawl
Resiliency
system-on-chip
security
Hardware
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