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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
time 5.052 ns
biblio
Hardware Design of Polynomial Multiplication for Byte-Level Ring-LWE Based Cryptosystem
Submitted by aekwall on Mon, 03/15/2021 - 12:10pm
NIST PQC Standardization Process
BRAMs
byte-level modulus
byte-level ring-LWE based cryptosystem
computational time-consuming block
DSPs
high-level synthesis based hardware design methodology
ideal lattice
LAC
multiplication core
high level synthesis
polynomial multiplication
ring learning with error problem
ring LWE
time 4.3985 ns
time 5.052 ns
time 5.133 ns
Vivado HLS compiler
Xilinx Artix-7 family FPGA
NIST
Scalability
lattice-based cryptography
Cryptography
Hardware
Table lookup
learning (artificial intelligence)
Resiliency
pubcrawl
Metrics
field programmable gate arrays
post quantum cryptography
timing
polynomials
Software algorithms
Compositionality
program compilers
compiler security
logic design
