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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
high level synthesis
biblio
Design Obfuscation versus Test
Submitted by aekwall on Mon, 10/04/2021 - 1:54pm
pubcrawl
Scalability
Resiliency
Human behavior
automatic test pattern generation
high level synthesis
integrated circuit design
logic locking
logic obfuscation
test
pattern locks
biblio
Hardware Design of Polynomial Multiplication for Byte-Level Ring-LWE Based Cryptosystem
Submitted by aekwall on Mon, 03/15/2021 - 12:10pm
NIST PQC Standardization Process
BRAMs
byte-level modulus
byte-level ring-LWE based cryptosystem
computational time-consuming block
DSPs
high-level synthesis based hardware design methodology
ideal lattice
LAC
multiplication core
high level synthesis
polynomial multiplication
ring learning with error problem
ring LWE
time 4.3985 ns
time 5.052 ns
time 5.133 ns
Vivado HLS compiler
Xilinx Artix-7 family FPGA
NIST
Scalability
lattice-based cryptography
Cryptography
Hardware
Table lookup
learning (artificial intelligence)
Resiliency
pubcrawl
Metrics
field programmable gate arrays
post quantum cryptography
timing
polynomials
Software algorithms
Compositionality
program compilers
compiler security
logic design
biblio
Hardware Steganography for IP Core Protection of Fault Secured DSP Cores
Submitted by aekwall on Mon, 11/09/2020 - 1:40pm
DSP based IP cores
vendor defined signature
transient fault secured IP cores
signature size
signature free approach
multimedia cores
IP core protection
IP core
high level synthesis
hardware steganography
fault secured DSP cores
Fault secure
entropy value
entropy thresholding
encoding rule
Resiliency
colored interval graph
IP piracy
Steganography
DSP
logic design
digital signal processing chips
Watermarking
industrial property
digital signatures
Entropy
graph theory
policy-based governance
composability
pubcrawl
biblio
Semantics-Directed Prototyping of Hardware Runtime Monitors
Submitted by grigby1 on Mon, 11/04/2019 - 12:35pm
ROP-style code reuse attacks
Monitoring
multiple memory accesses
pubcrawl
rapid-prototyping runtime monitors
reconfigurable architectures
resilience
Resiliency
rop attacks
Model driven development
Runtime
Scalability
security of data
Semantics
semantics-directed prototyping
software monitor
software-based attacks
Biomedical monitoring
Instruction sets
Human Factors
Human behavior
high level synthesis
hardware-based protection
Hardware Security
hardware runtime monitors
hardware monitor
Hardware
formal verification
embedded systems
embedded processor
embedded hardware
composability
building memory protection mechanisms
biblio
Improving Power amp; Latency Metrics for Hardware Trojan Detection During High Level Synthesis
Submitted by grigby1 on Mon, 12/10/2018 - 11:42am
Mathematical model
work factor metrics
Unroll Factor
Trojan horses
third party IP cores
Space exploration
semiconductor industry
secure IC design process
Scalability
resource allocation
Resiliency
resilience
pubcrawl
power metrics
power consumption
microprocessor chips
adders
latency metrics
invasive software
integrated circuits
integrated circuit design
integrated chip design
high level synthesis
hardware Trojan detection
hardware trojan
Hardware
design-for-trust techniques
design space exploration process
Design Space Exploration
datapath resource allocation
cuckoo search algorithm
Benchmark testing
biblio
Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm
Submitted by grigby1 on Wed, 09/12/2018 - 11:25am
SIMD
Program processors
Programmable SoC
pubcrawl
real-time on-line pattern search
real-time systems
resilience
Resiliency
Scalability
search problems
platform based design methodologies
string matching
system monitoring
system-on-chip
SystemC
TCP
TCP packets
Xilinx Zynq programmable SoC
Zynq
High-Le'vel Synthesis
Algorithm design and analysis
BM string search algorithm
Boyer-Moore
Boyer-Moore algorithm
computer network security
deep packet inspection
FPGA
Hardware
high level synthesis
Accelerator
high-level synthesis
Inspection
MISD parallelism
Network Monitoring
network security
parallel processing
Payloads
Platform Based Design
biblio
FPGA Based Hardware Acceleration of Sensor Matrix
Submitted by K_Hooper on Wed, 10/18/2017 - 10:15am
Activity Recognition
Compositionality
FPGA
hardware acceleration
high level synthesis
Human Factors
pubcrawl
sensing
Smart Grid Sensors
biblio
An efficient hardware implementation of few lightweight block cipher
Submitted by grigby1 on Wed, 03/08/2017 - 2:33pm
FPGA
sensor node
security system
Schedules
RFID
resource-efficient cryptographic incipient
radiofrequency identification
radio-frequency identification
pubcrawl170112
high level synthesis
Hardware Implementation
Hardware
Algorithm design and analysis
field programmable gate arrays
Field Programmable Gate Array (FPGA)
FeW lightweight block cipher
FeW cryptography algorithm
FeW Algorithm
Feistel structure
encryption
Cryptography
Ciphers
Block Cipher
biblio
A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs
Submitted by BrandonB on Wed, 05/06/2015 - 2:44pm
high level functionality verification
unified sequential equivalence checking approach
Sequential equivalence checking
sequence of states
RTL design verification
RTL design
Protocols
protocol specification implementation
Integrated circuit modeling
high-level models
high level synthesis
high level reference model
high level model
Abstracts
formal verification
formal technique
Formal Specification
electronic design automation
Educational institutions
design verification
design under verification
Data models
Computational modeling
computational margin
communication protocol
Calculators
